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TTRN012G53XE1

TTRN012G5 (2.5 Gbits/s) and TTRN012G7 (2.5 Gbits/s and 2.7 Gbits/s) Clock Synthesizer, 16:1 Data Multiplexer

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Preliminary Data Sheet

August 2000

TTRN012G5 and TTRN012G7

Clock Synthesizer, 16:1 Data Multiplexer

Clocking Modes and Timing Adjustments (continued)

Contra-Directional Clocking Mode (CLKMODE, PHADJ[1:0])

In the contra-directional clocking mode (CLKMODE = 1), the data is sampled with the internal 2.5 GHz clock at the

time of the falling edge of CK155P (see Figure 8 on page 19 for timing details). The device sends a 155 MHz clock

with one of four user-selectable phases out to the upstream device for clocking the data toward the device. The

user can program PHADJ[1:0] to adjust the phase of CK155 as a function of PWB layout and upstream device

propagation delay in order to meet the setup and hold time of the 155 Mbits/s data to the device. With a

PHADJ[1:0] = [11], the data is sampled by the internal CK2G5 clock at the falling edge of CK155P. PHADJ[1:0]

changes the phase of the CK155P clock without changing the input data sampling time. PHADJ[1:0] setting infor-

mation is given in Table 7, and the phase relationship of CK155 for each PHADJ[1:0] setting is shown in Figure 6.

Table 7. PHADJ Settings for CK155 Output Clock (Contra-Clocking Mode)

Input Pins

PHADJ1

PHADJ0

1

1

1

0

0

1

0

0

Phase

(See part A of Figure 6.)

(See part B of Figure 6.)

(See part C of Figure 6.)

(See part D of Figure 6.)

A. (0 DEG.)

B. (–90 DEG.)

C. (–180 DEG.)

D. (–270 DEG.)

TIME

Figure 6. CK155 Phase Relation vs. PHADJ Setting

5-8064(F)r.2

Lucent Technologies Inc.

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