E
4-MBIT SmartVoltage BOOT BLOCK FAMILY
3.0
INPUT
1.5
TEST POINTS
1.5 OUTPUT
0.0
NOTE:
AC test inputs are driven at 3.0V for a logic “1” and 0.0V for a logic “0.” Input timing begins, and output timing ends, at 1.5V.
Input rise and fall times (10% to 90%) <10 ns.
0530_12
Figure 12. 3.3V Inputs and Measurement Points
2.4
2.0
INPUT
TEST POINTS
2.0
OUTPUT
0.8
0.8
0.45
NOTE:
AC test inputs are driven at VOH (2.4 VTTL) for a logic “1” and VOL (0.45 VTTL) for a logic “0.” Input timing begins at VIH (2.0 VTTL)
and VIL (0.8 VTTL) . Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns.
0530_13
Figure 13. 5V Inputs and Measurement Points
DEVICE
UNDER
TEST
VCC
R1
CL
R2
Test Configuration Component Values
Test Configuration
3.3V Standard Test
CL (pF) R1 (Ω) R2 (Ω)
50
990 770
5V Standard Test
100 580 390
OUT
5V High-Speed Test
30
580 390
NOTE: CL includes jig capacitance.
NOTE: See table for component values.
Figure 14. Test Configuration
0530_14
PRELIMINARY
33