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TEA0679

I2C-bus controlled dual Dolby* B-type noise reduction circuit for playback applications

Philips Electronics 

Philips Semiconductors

I2C-bus controlled dual Dolby* B-type noise

reduction circuit for playback applications

Product specification

TEA0679T

FUNCTIONAL DESCRIPTION

The following functions can be controlled via the I2C-bus:

• Equalization time constant switching

• Head switching

• Automatic Music Search (AMS) modes and blank skip

• Noise Reduction (NR) on/off switching

• Mute switching

• Equalization amplifier gain adjustment

• Output offset adjustment.

Dolby B noise reduction only operates correctly if the 0 dB

Dolby level is adjusted at 387.5 mV. The gain adjustment

can also be used to change the AMS level detector

threshold. The IC is able to generate an internal power-on

reset to guarantee a proper start-up behaviour.

Two of the above functions can be controlled via separate

pins (optional), if required.

Head switching is achieved when pin HS is connected to a

LOW level (input IN2 active) or connected to a HIGH level

(input IN1 active).

Equalization time constant switching (70 or 120 µs) is

achieved when pin EQS is connected to a LOW level

(70 µs) or connected to a HIGH level (120 µs).

If I2C-bus control is used the respective external function

control pin has to be left open-circuit. When open-circuit

the current state of the function can be observed at these

pins.

Automatic Music Search (AMS) modes and blank skip

If AMS is active (search mode bits SMOD1 = 1 and

SMOD0 = 0 or 1) the NR function is internally switched off

and the equalization time constant is internally forced to

70 µs. The signals of both channels are full-wave rectified

and then added. This means that even if one channel

appears inverted to the other channel the normal AMS

function is ensured.

It is possible to choose between the AMS scan and the

AMS latch mode via the I2C-bus. Due to the usage of an

internal flip-flop the switching from one mode to the other

must be done via the AMS off state. This guarantees an

appropriate flip-flop reset:

• Start from the initial AMS off state (SMOD1 = 0 and

SMOD0 = 0 or 1)

• Enable the desired AMS operation mode: AMS latch

mode (SMOD1 = 1 and SMOD0 = 0) or AMS scan mode

(SMOD1 = 1 and SMOD0 = 1).

For further information on music search see Figs 4 to 8.

If blank skip is active (SMOD1 = 0 and SMOD0 = 1)

periods of music can be detected in the playback mode

using the AMS pin as the detector output. It is possible to

defeat this function via the I2C-bus (SMOD1 = 0 and

SMOD0 = 0). For further information on blank skip

see Figs 9 and 10.

Offset adjustment procedure

The offset adjustment is performed using two bits in the

I2C-bus write byte 0. The offset monitor bit OMOR enables

the AMS output to indicate whether the selected offset

value is positive or negative. The channel select bit OFCH

selects the channel (A or B) which is currently monitored

by the output at pin AMS. The monitoring needs a few

microseconds until the output result is valid. A complete

offset adjustment is performed in the following way:

• Adjust the output to Dolby level using the I2C-bus

controlled equalization gain adjustment

• Enable the offset monitor and select the channel to be

monitored by transmitting the bits OMOR = 1 and OFCH

(0 = Channel A, 1 = Channel B) to the IC

• If the monitor output (pin AMS) is LOW send the next

offset value OFFCHA or OFFCHB one offset step below

the last valid value. If the monitor output (pin AMS) is

HIGH send the next offset value OFFCHA or OFFCHB

one offset step above the last valid value

• Repeat the last two steps until the monitor output

changes its polarity

• If necessary store the transmitted digital offset value for

the selected channel.

The start value is either set by the power-on reset or the

last I2C-bus transmission. The offset adjustment can be

performed during the power-on reset condition and also

each time the tape driver is not active. A complete digital

offset data set consists of four values: one for each head

(head 1 and head 2) in each channel. After an offset value

transmission the IC stores one value for channel A and

one value for channel B. If a head switch is performed

these values have to be updated via the I2C-bus for the

alternative head.

1998 Nov 12

5

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