TEA0679T Ver la hoja de datos (PDF) - Philips Electronics
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Fabricante
TEA0679T
Philips Electronics
TEA0679T Datasheet PDF : 40 Pages
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Philips Semiconductors
I2C-bus controlled dual Dolby* B-type noise
reduction circuit for playback applications
Product specification
TEA0679T
Description of the principle timing diagram for AMS latch mode with initial input signal (see Fig.8)
This is similar to the description in Section “Description of the principle timing diagram for AMS scan mode with initial
input signal (see Fig.6)”. It only differs in its rise time tr and a release of its internal latch when voltage Vt exceeds the
upper threshold between t0 and t1. The initial procedure is now completed.
The following behaviour does not differ from the description in Section “Description of the principle timing diagram for
AMS latch mode without initial input signal (see Fig.7)”.
handbook, full pagewidth AMS on
Vin
td
tb < tr
tf
tp < td
Vl
level threshold
Vref
Vt
upper threshold
(hysteresis)
time threshold
internal H
latch status
L
VAMSEQ
4.5 V
output signal
to power FET
t0 t1
t5 t6
t7 t8 t9 t10
t11 t12 t13 t14
t15
tr = rise time; td = delay time; tb = burst time; tp = pause time; tf = fall time.
Fig.8 AMS latch mode with initial input signal.
1998 Nov 12
15
t
Vl: voltage at
level detector
input
pin 8 (CONTRA)
t
Vt: voltage at
time detector
input
pin 25 (CONTRB)
t
t
t
MHB123
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