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TDA9855

I2C-bus controlled BTSC stereo/SAP decoder and audio processor

Philips Electronics 

Philips Semiconductors

I2C-bus controlled BTSC stereo/SAP

decoder and audio processor

Product specification

TDA9855

Notes to the characteristics

1. The oscillator is designed to operate together with a MURATA resonator CSB503F58 for TDA9855. Change of the

resonator supplier is possible, but the resonator specification must be close to CSB503F58 for TDA9855.

2. The internal SAP carrier level is determined by the composite input level and the level adjustment gain.

3. Select in to input line control.

4. Crosstalk: 20 log V--V---b-o-u--(-s-r-(m--p---s--p)--)

5. The transmission contains:

a) Total initialization with MAD and SAD for volume and 11 DATA words, see also definition of characteristics

b) Clock frequency = 50 kHz

c) Repetition burst rate = 400 Hz

d) Maximum bus signal amplitude = 5 V (p-p).

6. The listed pin voltage corresponds with typical gain steps of +6 dB, +3 dB, 0 dB, −6 dB and −15 dB.

7. Attack time constant = CAV × Ratt.

CAV

×

0.76

V







10 –----G2---0--v--1-

–

10

–----G2---0--v--2-











8. Decay time = -------------------------------------I--d---e---c--------------------------------------

Example: CAV = 4.7 µF; Idec = 2 µA; Gv1 = −9 dB; Gv2 = +6 dB → decay time results in 4.14 s.

9. When reset is active the GMU-bit (general mute) and the LMU-bit (LINE OUT mute) is set and the I2C-bus receiver

is in the reset position.

10. The AC characteristics are in accordance with the I2C-bus specification. The maximum clock frequency is 100 kHz.

Information about the I2C-bus can be found in the brochure “The I2C-bus and how to use it”

(order number 9398 393 40011).

1997 Nov 04

21

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