TDA7500A Ver la hoja de datos (PDF) - STMicroelectronics

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TDA7500A

DIGITAL AM/FM SIGNAL PROCESSOR

STMicroelectronics 

TDA7500A

PIN DESCRIPTION (continued)

N°

Name

Type

Description

46 SRA<9>

O DSP SRAM Address Line<9> (Output)/DSP DRAM Address

Line<9> (Output). This pin acts as the EMI address line 9 in both

SRAM Mode and DRAM Mode

47 SRA<10>

O DSP SRAM Address Line<10> (Output)/DSP DRAM Address

Line<10> (Output). This pin acts as the EMI address line 10 in

both SRAM Mode and DRAM Mode

48 SRA<11>

O DSP SRAM Address Line<11> (Output)/DSP DRAM Address

Line<11> (Output). This pin acts as the EMI address line 11 in

both SRAM Mode and DRAM Mode

49 SRA<12>

O DSP SRAM Address Line<12> (Output)/DSP DRAM Address

Line<12> (Output). This pin acts as the EMI address line 12 in

both SRAM Mode and DRAM Mode

50 CGND2

Ground pin dedicated to the digital circuitry.

51 CVDD2

Supply pin dedicated to the digital circuitry.

52 SRA<13>

O DSP SRAM Address Line<13> (Output)/DSP DRAM Address

Line<13> (Output). This pin act as the EMI address line 13 in

both SRAM Mode and DRAM Mode.

53 SRA<14>

O DSP SRAM Address Line<14> (Output)/DSP DRAM Address

Line<14> (Output). This pin act as the EMI address line 14 in

both SRAM Mode and DRAM Mode.

54 SRA<15>

O DSP SRAM Address Line<15> (Output)/DSP DRAM Address

Line<15> (Output). This pin act as the EMI address line 15 in

both SRAM Mode and DRAM Mode.

55 SRA<16>/DSP0_GPIO8

O DSP SRAM Address Line<16> (Output)/DSP DRAM Address

Line<16> (Output)/General Purpose I/O (Input/Output). This pin

acts as the EMI address line 16 in both SRAM Mode and DRAM

Mode. Optionally it can be used as general purpose I/O

controlled by DSP0. After reset the state of this pin is read by the

boot SW to select the boot mode (Refer to HW/SW maual).

56 DWR

O DSP SRAM Write Enable (Output)/DRAM Write Enable

(Output). This pin serves as the write enable for the EMI in both

DRAM and SRAM Mode (active low). To be connected to R/W of

the RAM.

57 DRD

O DSP SRAM Read Enable(Output)/DRAM Read Enable (Output).

This pin serves as the read enable for the EMI in both DRAM

and SRAM Mode (active low). To be connected to R/W of the

RAM.

58 CASALE

O DSP DRAM Column Address Strobe (Output). When in DRAM

Mode this pin acts as the column address strobe.

59 SDO<2>/SRA<17>/DSP1_GPIO<8> O SAI Outputs (Output)/EMI SRAM Address Line<17> (Output)/

General Purpose I/O (Input/Output). One stereo channel SAI

data output in SAI mode. EMI address line 17 in SRAM Mode.

Optionally it can be used as a general purpose I/O.

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