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TC7129CLW Ver la hoja de datos (PDF) - Microchip Technology

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TC7129CLW Datasheet PDF : 28 Pages
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4.8 Successive Integration
The successive integration technique picks up where
dual-slope conversion ends. The overshoot voltage
shown in Figure 4-9 (called the “integrator residue
voltage”) is measured to obtain a correction to the initial
count. Figure 4-10 shows the cycles in a successive
integration measurement.
The waveform shown is for a negative input signal. The
sequence of events during the measurement cycle is
shown in Table 4-1.
TABLE 4-1: MEASUREMENT CYCLE
SEQUENCE
Phase
Description
INT1 Input signal is integrated for fixed time (1000 clock
cycles on 2V scale, 10,000 on 200 mV).
DE1 Integrator voltage is ramped to zero. Counter
counts up until zero-crossing to produce reading
accurate to 3-1/2 digits. Residue represents an
overshoot of the actual input voltage.
REST Rest; circuit settles.
X10 Residue voltage is amplified 10 times and
inverted.
DE2 Integrator voltage is ramped to zero. Counter
counts down until zero-crossing to correct reading
to 4-1/2 digits. Residue represents an undershoot
of the actual input voltage.
REST Rest; circuit settles.
X10 Residue voltage is amplified 10 times and
inverted.
DE3 Integrator voltage is ramped to zero. Counter
counts up until zero-crossing to correct reading to
5-1/2 digits. Residue is discarded.
TC7129
4.9 Digital Auto-Zeroing
To eliminate the effect of amplifier offset errors, the
TC7129 uses a digital auto-zeroing technique. After the
input voltage is measured as described above, the
measurement is repeated with the inputs shorted
internally. The reading with inputs shorted is a
measurement of the internal errors and is subtracted
from the previous reading to obtain a corrected
measurement. Digital auto-zeroing eliminates the need
for an external auto-zeroing capacitor used in other
ADCs.
4.10 Inside the TC7129
Figure 4-11 shows a simplified block diagram of the
TC7129.
© 2006 Microchip Technology Inc.
DS21459D-page 13

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