T5743 Ver la hoja de datos (PDF) - Atmel Corporation

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T5743

UHF ASK/FSK Receiver

Atmel Corporation 

T5743

Figure 11. Timing Diagram for Complete Successful Bit Check

( Number of checked Bits: 3 )

Bit check ok

IC_ACTIVE

Bit check

Dem_out

Data_out (DATA)

TStart-up

Start-up mode

1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit

TBit-check

Bit-check mode

Receiving mode

Bit-check Mode

Configuring the Bit Check

In bit-check mode the incoming data stream is examined to distinguish between a valid

signal from a corresponding transmitter and signals due to noise. This is done by subse-

quent time frame checks where the distances between two signal edges are

continuously compared to a programmable time window. The maximum count of this

edge-to-edge tests before the receiver switches to receiving mode is also

programmable.

Assuming a modulation scheme that contains two edges per bit, two time frame checks

are verifying one bit. This is valid for Manchester, Bi-phase and most other modulation

schemes. The maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the

variable NBit-check in the OPMODE register. This implies 0, 6, 12 and 18 edge to edge

checks respectively. If NBit-check is set to a higher value, the receiver is less likely to

switch to receiving mode due to noise. In the presence of a valid transmitter signal, the

bit check takes less time if NBit–check is set to a lower value. In polling mode, the bit-check

time is not dependent on NBit-check. Figure 11 shows an example where 3 bits are tested

successfully and the data signal is transferred to Pin DATA.

According to Figure 12, the time window for the bit check is defined by two separate

time limits. If the edge-to-edge time tee is in between the lower bit-check limit TLim_min and

the upper bit-check limit TLim_max, the check will be continued. If tee is smaller than

TLim_min or tee exceeds TLim_max, the bit check will be terminated and the receiver

switches to sleep mode.

Figure 12. Valid Time Window for Bit Check

1/fSig

Dem_out

tee

TLim_min

TLim_max

4569A–RKE–12/02

For best noise immunity it is recommended to use a low span between TLim_min and

TLim_max. This is achieved using a fixed frequency at a 50% duty cycle for the transmitter

preburst. A “11111...” or a “10101...” sequence in Manchester or Bi-phase is a good

choice concerning that advice. A good compromise between receiver sensitivity and

susceptibility to noise is a time window of ±25% regarding the expected edge-to-edge

time tee. Using pre-burst patterns that contain various edge-to-edge time periods, the

bit-check limits must be programmed according to the required span.

The bit-check limits are determined by means of the formula below.

13

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