LH5481 Ver la hoja de datos (PDF) - Sharp Electronics

Número de pieza

componentes Descripción

Fabricante

LH5481

Cascadable 64 × 8 FIFO Cascadable 64 × 9 FIFO

Sharp Electronics 

LH5481/91

FIFO EXPANSION (cont’d)

64 × 8 / 64 × 9 FIFO

HF/AFE

SHIFT IN

INPUT READY

DATA IN

HF/AFE

SI

OR

IR

SO

DI0

DO0

DI1

DO1

DI2 64 x 8/9 DO2

DI3

DO3

DI4

DO4

DI5

DO5

DI6

DO6

DI7

DO7

DI8

DO8

MR

SI

OR

IR

SO

DI0

DO0

DI1

DO1

DI2

DI3

256 x 8/9

DO2

DO3

DI4

DO4

DI5

DO5

DI6

DO6

DI7

DO7

DI8

DO8

MR

OUTPUT READY

SHIFT OUT

DATA OUT

MR

Figure 17. 128 × 8/9 Configuration

5481-17

FIFOs are expandable in depth and width. However,

in forming wider words, external logic is required to gen-

erate composite Input Ready and Output Ready flags.

This is due to the variation of delays of the FIFOs. For

example, the circuit of Figure 16 uses simple AND gates

as the external IR and OR generators. More complex logic

may be required if fallthrough and bubblethrough pulses

are needed by the external system.

FIFOs can be easily cascaded to any desired depth,

as illustrated in Figure 17. The handshaking and associ-

ated timing between the FIFOs are handled by the inher-

ent timing of the devices.

NOTES:

1. When the memory is empty, the last word read remains on the out-

puts until Master Reset is strobed, or a new data word bubbles

through to the output. However, OR remains LOW, indicating

that the data word at the output is not valid.

2. When the output data word changes as a result of a pulse on SO,

the OR signal always goes LOW before the output data word

changes and stays LOW until a new data word has appeared at

the outputs. Anytime OR is HIGH, there is valid stable data on

the outputs.

3. All SHARP FIFOs can be cascaded with other SHARP FIFOs of

the same architecture (i.e., 64 × 8/9 with 64 × 8/9). However,

they may not cascade with FIFOs from other manufacturers.

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