SAA7705H Ver la hoja de datos (PDF) - Philips Electronics
Número de pieza
componentes Descripción
Fabricante
SAA7705H Datasheet PDF : 60 Pages
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Philips Semiconductors
Car radio Digital Signal Processor (DSP)
Preliminary specification
SAA7705H
7 PINNING
SYMBOL
VDACP
VDACN1
FML
AML
POM
RRV
RRI
RLI
RLV
VSSA2
VDDA2
VREFDA
FRV
FRI
FLI
FLV
TP1
TP2
TP3
TP4
TP5
VDDD5V1
VSSD5V1
CD2WS
CD2DATA
CD2CL
CD1WS
CD1DATA
CD1CL
IISCLK
IISIN1
IISIN2
IISWS
IISOUT1
IISOUT2
VDDD5V2
VSSD5V2
DSPIN1
DSPIN2
PIN PIN TYPE
1 AP2D
2 AP2D
3 AP2D
4 AP2D
5 AP2D
6 AP2D
7 AP2D
8 AP2D
9 AP2D
10 APVSS
11 APVDD
12 AP2D
13 AP2D
14 AP2D
15 AP2D
16 AP2D
17 BT4CR
18 BT4CR
19 BT4CR
20 BT4CR
21 IBUFD
22 VDDE5
23 VSSE5
24 IBUFD
25 IBUFD
26 IBUFD
27 IBUFD
28 IBUFD
29 IBUFD
30 BT4CR
31 IBUFD
32 IBUFD
33 BD4CR
34 BD4CR
35 BD4CR
36 VDDE5
37 VSSE5
38 IBUFD
39 IBUFD
DESCRIPTION
positive reference voltage for SCAD1, SCAD2, SCAD3 and level-ADC
ground reference voltage 1 for SCAD1, SCAD2, SCAD3 and level-ADC
FM level input; via this pin the level of the FM signal is fed to the SAA7705H; the
level information is needed for a correct functioning of the weak signal behaviour
AM level input; via this pin the level of the AM signal is fed to the SAA7705H
power-on mute of the QDAC; timing is determined by an external capacitor
rear right audio voltage output of the QDAC
rear right audio current output of the QDAC
rear left audio current output of the QDAC
rear left audio voltage output of the QDAC
ground supply for the analog part of the QDAC
positive supply for the analog part of the QDAC
decoupling for voltage reference of the analog part of the QDAC
front right audio voltage output of the QDAC
front right audio current output of the QDAC
front left audio current output of the QDAC
front left audio voltage output of the QDAC
test pin, used in factory test mode, must not be connected
test pin, used in factory test mode, must not be connected
test pin, used in factory test mode, must not be connected
test pin, used in factory test mode, must not be connected
test pin, used in factory test mode, must be connected to VDDD5V
positive supply 1 for peripheral cells
ground supply 1 for peripheral cells
word select input 2 from a digital audio source (I2S-bus or LSB-justified format)
left or right data input 2 from a digital audio source (I2S-bus or LSB-justified format)
clock input 2 from a digital audio source (I2S-bus or LSB-justified format)
word select input 1 from a digital audio source (I2S-bus or LSB-justified format)
left or right data input 1 from a digital audio source (I2S-bus or LSB-justified format)
clock input 1 from a digital audio source (I2S-bus or LSB-justified format)
clock output to extra DSP chip (I2S-bus)
data input channel 1 (front) from extra DSP chip (I2S-bus)
data input channel 2 (rear) from extra DSP chip (I2S-bus)
word select input or output for extra DSP chip (I2S-bus)
data output to extra DSP chip (I2S-bus)
subwoofer output (I2S-bus)
positive supply 2 for peripheral cells
ground supply 2 for peripheral cells
digital input 1 of the DSP core (flag F0 of the status register)
digital input 2 of the DSP core (flag F1 of the status register)
1999 Aug 16
7
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