Figure 3. Zoom for OUTn showing tS and tF OUT
tF OUT
OUTn
90%
STV7620S/M/F
Figure 4. Test configuration
VPP=VSSP
VDOUTH
tS
IDOUTH
10%
VPP=VSSP
VSSP
VSSP
VDOUTL
Output sinking current as positive value, sourcing current as negative value
IDOUTL
11 TESTED WAFER DISCLAIMER
All wafers are tested and guaranteed to comply with all datasheet limits up to the point of wafer sawing for
a period of ninety (90) days from the delivery date.
We remind you that it is the customer’s responsibility to test and qualify their application in which the die
is used. ST Microelectronics is ready to support the customer when qualifying the product.
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