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STPIC44L02

4 CHANNEL SERIAL AND PARALLEL LOW SIDE PRE-FET DRIVER

STMicroelectronics 

STPIC44L02

SWITCHING CHARACTERISTICS (VCC=5V, VBAT=5V, TC= 25°C, unless otherwise specified.)

Symbol

Parameter

Test Conditions

Min. Typ. Max.

t(STBFM)

t(STBDG)

tPLH

tPHL

tr1

tf1

f(SCLK)

trf(SB)

tW)

tsu1

tpd1

tpd2

tpd3

tr2

tf2

tr3

tf3

Short to Battery, Shorted

Load, Open Load Fault

Mask Time

(see figures 16, 17)

Short to Battery, Shorted

Load, Deglitch Time

(see figures 16, 17)

Propagation Turn-On Delay C(gate) = 400pF

Time, CS or IN0-IN3 to

Gate0-Gate3

Propagation Turn-Off Delay C(gate) = 400pF

Time, CS or IN0-IN3 to

Gate0-Gate3

Rise Time, Gate0-Gate3

Fall Time, Gate0-Gate3

Serial Clock Frequency

C(gate) = 400pF

C(gate) = 400pF

Refresh Time Short to

Battery

(see figure 16)

Refresh pulse width Short (see figure 16)

to Battery

Setup Time CS ↓ to SCLK ↓ (see note 1)

(see figure 4)

Propagation Delay Time CS RL = 10KΩ

to SDO Valid

(see figure 6)

CL = 200pF

Propagation Delay Time

SCLK to SDO Valid

Propagation Delay Time CS RL = 10KΩ

to SDO 3-State

(see figure 6)

CL = 50pF

Rise Time, SDO 3-State to RL = 10KΩ to GND CL = 200pF

SDO Valid

Over Battery Fault (see figure 7)

Fall Time, SDO 3-State to RL = 10KΩ to GND CL = 200pF

SDO Valid

No Fault

(see figure 8)

Rise Time, FLT

RL = 10KΩ

(see figure 9)

CL = 50pF

Rise Time, FLT

RL = 10KΩ

(see figure 9)

CL = 50pF

60

12

3.5

4

1.5

2

10

10

68

10

40

20

2

30

20

1.2

15

Note 1: The td1 is referred to the falling edge of the first clock after the CS falls down

Unit

µs

µs

µs

µs

µs

µs

MHz

ms

µs

ns

ns

ns

µs

ns

ns

µs

ns

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