STA323W Ver la hoja de datos (PDF) - STMicroelectronics

Número de pieza

componentes Descripción

Fabricante

STA323W

2.1-channel high-efficiency digital audio system

STMicroelectronics 

STA323W

Pin out

Table 5.

Pin

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

Pin list (continued)

Type

Name

I/O

GND_CLEAN

I/O

GND_REG

I/O

VDD_REG

I/O

VL

I

CONFIG

I

RESET

I

SCL

I/O

SDA

-

RESERVED

I

PLL_FILTER

I

XTI

I/O

GNDA

I/O

VDDA

I

SDI_12

I/O

LRCKI

I

BICKI

I/O

GND

I/O

VDD

I/O

VSS

I/O

VCC_SIGN

Description

Reference ground

Substrate ground

Logic supply

Logic supply to power section

Logic levels

Reset

I2C serial clock

I2C serial data

Reserved test pin must be connected to ground

Connection to PLL filter

PLL input clock

Analog ground

Analog supply 3.3

I2S serial data channels 1 and 2

I2S left/right clock,

I2S serial clock

Digital ground

Digital supply 3.3 V

5 V regulator referred to Vcc

5 V regulator referred to ground

3.2

Pin description

OUT1A, 1B, 2A and 2B (pins 16, 10, 9 and 3)

The half-bridge PWM outputs 1A, 1B, 2A and 2B provide the inputs signals to the speakers.

RESET (pin 22)

Driving RESET low sets all outputs low and returns all register settings to their default

(reset) values. The reset is asynchronous to the internal clock.

SDA, SCL (pins 24, 23)

The SDA (I2C Data) and SCL (I2C Clock) pins operate according to the I2C specification

(See Chapter 6 on page 33.) Fast-mode (400 kB/s) I2C communication is supported.

VDDA, GNDA (pins 29,28)

The phase locked loop power is applied here. This +3.3V supply must be well decoupled

and filtered for good noise immunity since the audio performance of the device depends

upon the PLL circuit.

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