ST7573 Ver la hoja de datos (PDF) - Sitronix Technology Co., Ltd.
Número de pieza
componentes Descripción
Fabricante
ST7573 Datasheet PDF : 46 Pages
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ST7573
LCD driving voltage for segments.
VGI is the VG power source for the LCD driver. If using external VG, apply
external power source on these pads.
VGI, VGO, VGS Power
7
VGO is the internal VG regulator output pad.
VGS is the feedback for the internal VG voltage compensation circuit.
They should be separate in ITO and be connected together by FPC.
VM
Power LCD driving voltage for commons.
3
CONFIGURATION PIN
Data format (MSB on top or LSB on top).
MLB
I
MLB=”H”, MSB on top (D7 on top);
1
MLB=”L”, LSB on top (D0 on top).
Set power mode. This pin will change the V0 (Vop) formula parameter.
PM
I
V0=( a + VOP[6:0] x b )
1
PM=”L”, a=3.0V, b=0.03V;
PM=”H”, a=4.5V, b=0.03V.
TEST PIN
T0~T8: left them open.
T0…T11
Test T9 must connect to VSS.
12
T10 and T11 must connect to VDD.
The unused pins should be left floating.
The Microprocessor Interface pins should not be left floating under any operation mode.
Recommend I/O pins ITO Resistance Limitation
Pin Name
VRS, T[8:0]
VSS
VDD
VDD2
V0 (V0I + V0O + V0S), XV0 (XV0I + XV0O + XV0S), VG (VGI + VGO + VGS), VM
CSB, A0, /RD, /WR, D[7:0]
PS[2:0], OSC*1, MLB, T[11:9]
RESB
ITO Resistance
Floating
<100Ω
<100Ω
<100Ω
<500Ω
<1KΩ
<5KΩ
<10KΩ
Notes:
1. If using internal clock, OSC is connect to VDD and the limitation of ITO resistance will be “No Limitation”.
If using external clock, the ITO resistance of OSC should be kept lower than 500Ω to keep the clock signal quality.
Ver 1.0b
10/46
2007/07/12
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