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PIC16C62X

EPROM-Based 8-Bit CMOS Microcontroller

Microchip Technology 

PIC16C62X

4.2.2.4 PIE1 REGISTER

This register contains the individual enable bit for the

comparator interrupt.

FIGURE 4-11: PIE1 REGISTER (ADDRESS 8CH)

U-0

R/W-0

U-0

U-0

U-0

U-0

—

CMIE

—

—

—

—

bit7

bit 7: Unimplemented: Read as '0'

bit 6:

CMIE: Comparator Interrupt Enable bit

1 = Enables the Comparator interrupt

0 = Disables the Comparator interrupt

bit 5-0: Unimplemented: Read as '0'

U-0

U-0

—

—

R = Readable bit

bit0 W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

4.2.2.5 PIR1 REGISTER

This register contains the individual flag bit for the

comparator interrupt.

Note:

Interrupt flag bits get set when an interrupt

condition occurs regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User

software should ensure the appropriate

interrupt flag bits are clear prior to enabling

an interrupt.

FIGURE 4-12: PIR1 REGISTER (ADDRESS 0CH)

U-0

R/W-0

U-0

U-0

U-0

U-0

—

CMIF

—

—

—

—

bit7

bit 7: Unimplemented: Read as'0'

bit 6:

CMIF: Comparator Interrupt Flag bit

1 = Comparator input has changed

0 = Comparator input has not changed

bit 5-0: Unimplemented: Read as '0'

U-0

U-0

—

—

R = Readable bit

bit0 W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

© 1998 Microchip Technology Inc.

Preliminary

DS30235G-page 21

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