TDA8980 Ver la hoja de datos (PDF) - Philips Electronics
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TDA8980 Datasheet PDF : 36 Pages
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Philips Semiconductors
ATSC Digital Terrestrial TV
demodulator/decoder
Objective specification
TDA8961
FUNCTIONAL DESCRIPTION
The internal architecture of the TDA8961 basically
comprises two parts:
• The front-end: containing the AGC, carrier recovery,
half Nyquist filter, symbol timing recovery, sync recovery
and adaptive equalization sections.
• The back-end: containing the NTSC co-channel
rejection filter, trellis decoder, de-interleaver, the Reed
Solomon decoder and de-randomizer sections.
Sample rate converter
INTRODUCTION
The sample rate converter section changes the incoming
data frequency of 36 MHz to an internal sampling
frequency of twice the symbol rate.
The 10-bit wide data from either the TDA8980 or a
stand-alone A/D converter (TDA8763A is recommended)
arrives at the sample rate converter input of the TDA8961
via inputs ADIN9 to ADIN0. The format of the incoming
samples can be programmed by the status of I2C-bus
bit AD_FMT (see Table 9). The format can be either two’s
complement or binary. The default setting is binary to
comply with the TDA8980.
Fine AGC
The fine AGC section controls the gain of analog signals
over a range of ±20 dB.
The level of the signal at pins ADIN9 to ADIN0 is
monitored and an average level from several samples is
acquired. The default number of samples is 64, but this
value can be set to 256 by setting I2C-bus
bit AGC_SAMPLES (see Table 10). A comparator
compares the level of the filtered signal with a threshold
level represented by a signed four-bit value set by I2C-bus
bits AGC_TR_LOW. The comparator output determines
the level at pin AGCOUT which is used to either charge or
discharge an off-chip ideal integrator, which in turn,
controls the gain of the tuner front-end module.
To make the level at pin AGCOUT compatible with the
AGC circuits in other devices, the comparator output can
be inverted by setting I2C-bus bit AGC_DIR (see
Table 10). The default value of bit AGC_DIR is 0 making
the output at pin AGCOUT compatible with the AGC circuit
in the TDA8980. The levels at pin AGCOUT with respect
to the value of bit AGC_DIR are shown in Table 2.
The AGC section can be reset by setting I2C-bus
bit AGC_RESET (see Table 8).
PINNING
The functions of the input interface pins are given in
Table 1. If a stand-alone A/D converter is used, pin CLK36
is connected externally to pin ADCLK.
Table 1 Input interface
NAME
ADIN9 to ADIN0
ADCLK
CLK36
Table 2 AGC
FILTER OUTPUT LEVEL
Above threshold
Below threshold
Above threshold
Below threshold
Equal to threshold
FUNCTION
10-bit data input (from external A/D converter)
36 MHz clock signal input
clock signal output for sampling incoming data (to external A/D converter)
COMPARATOR OUTPUT
1
0
1
0
Z
I2C-bus
bit AGC_DIR
0
0
1
1
0
Pin AGCOUT
1
0
0
1
Z
2000 May 19
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