CXA3250AN
3-1) Address settings
Up to four addresses can be selected by the hardware bit settings, so that multiple PLL can exist within
one system.
The responding address can be set according to the ADSW/CE pin voltage.
Address
1
1
0
Hardware bits
CE pin voltage
0 to 0.1 VCC
OPEN or
0.2 VCC to 0.3 VCC
0.4 VCC to 0.6 VCC
0.9 VCC to VCC
0
0
MA1 MA0 R/W
MA1
0
0
1
1
MA0
0
1
0
1
3-2) Write mode
Write mode is used to receive various data. In this mode, byte 1 contains the address data, bytes 2 and
3 contain the frequency data, byte 4 contains the control data, and byte 5 contains the band switch data.
These data are latch transferred in the manner of byte 1, byte 2 + byte 3, and byte 4 + byte 5.
When the correct address is received and acknowledged, the data is recognized as frequency data if the
first bit of the next byte is “0”, and as control data and band switch data if this bit is “1”.
Also, when data transmission is stopped part-way, the previously programmed data is valid. Therefore,
once the control and band switch data have been programmed, 3-byte commands consisting of the
address and frequency data are possible.
Further, even if the I2C bus stop conditions are not met, data can be input by sending the start
conditions and the new address.
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