DS2405P(1999) Ver la hoja de datos (PDF) - Dallas Semiconductor -> Maxim Integrated

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componentes Descripción

Fabricante

DS2405P
(Rev.:1999)

Addressable Switch

Dallas Semiconductor -> Maxim Integrated 

DS2405

READ/WRITE TIME SLOTS

The definitions of write and read time slots are illustrated in Figure 6. All time slots are initiated by the

master driving the data line low. The falling edge of the data line synchronizes the DS2405 to the master

by triggering a delay circuit in the DS2405. During write time slots, the delay circuit determines when the

DS2405 will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay circuit

determines how long the DS2405 will hold the data line low overriding the “1” generated by the master.

If the data bit is a 1, the device will leave the read data time slot unchanged.

READ/WRITE TIMING DIAGRAM Figure 6

Write-1 Time Slot

RESISTOR

MASTER

Write-0 Time Slot

60 µs ≤tSLOT < 120 µs

1 µs ≤tLOW1 < 15 µs

1 µs ≤tREC < ∞

60 µs ≤tLOW0 < tSLOT < 120 µs

1 µs ≤tREC < ∞

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