SLA7062 Ver la hoja de datos (PDF) - Allegro MicroSystems

Número de pieza

componentes Descripción

Fabricante

SLA7062

UNIPOLAR STEPPER-MOTOR TRANSLATOR/DRIVERS

Allegro MicroSystems 

SLA7060M THRU SLA7062M

UNIPOLAR STEPPER-MOTOR

TRANSLATOR/DRIVERS

Applications Information (cont’d)

Reference voltage. In the Typical Application shown,

resistors R1 and R2 set the reference voltage as:

VREF = (VDD x R2)/(R1 + R2)

The trimming of R2 allows for the resistor tolerances

and REF input current. The sum of R1+R2 should be less

than 50 kΩ to minimize the effect of IREF.

Minimum output current. The Series SLA7060M uses

fixed off-time PWM current control. Due to internal logic

and switching delays, the actual load current peak will be

slightly higher than the calculated ITRIP value (especially

for low-inductance loads). These delays, plus the mini-

mum recommended VREF, limit the minimum value the

current-control circuitry can regulate. An application with

this device should maintain continuous PWM control in

order to obtain optimum torque out of the motor. The

boundary of the load current (IO(min)) between continuous

and discontinuous operation is:

IO(min) = [(VM + VSD)/Rm] x [(1/etoff/[Rm x Lm]) - 1]

where

VM = load supply voltage

VF = body diode forward voltage

Rm = motor winding resistance

toff = PWM off time

Lm = motor winding inductance

To produce zero current in a motor, the REF input

should be pulled above 2 V, turning off all drivers.

Synchronous operation mode. If an external signal

is not available to control the synchronous operation

mode, a simple circuit can keep the SYNC input low while

the CLOCK input is active; the SYNC input will go high

(synchronous operation) when the CLOCK input stays low

(“hold”). The RC time constant determines the sync

trransition timing.

NOTE –The use of this function except at 0, 70.7, or

100%Itripmax (half-step positions 0 through 8) is not

recommended.

Temperature effects on FET outputs. Analyzing

safe, reliable operation includes a concern for the relation-

ship of NMOS on resistance to junction temperature.

Device package power calculations must include the

increase in on resistance (producing higher on voltages)

Continuous

mode

Discontinuous

mode

Sync. signal generator

1.6

1.4

1.2

1

0.8

0.6

0.4

0.2

0

-50

Io=1.0A

Io=0.7A

Io=0.5A

-25 0 25 50 75 100 125 150

Junction temperature in C

Normalized FET on resistance

115 Northeast Cutoff, Box 15036

12

Worcester, Massachusetts 01615-0036 (508) 853-5000

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