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SI4112G-BT

DUAL-BAND RF S YNTHESIZER WITH INTEGRATED VCOS FOR GSM AND GPRS WIRELESS COMMUNICATIONS

Silicon Laboratories 

Si4133G

Control Registers

Table 10. Register Summary

Register Name

Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit

17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 Main

0 0 0 0 AUXSEL 0 0 0 0 0 0 LPWR 0 AUTO 0 1 0

Configuration

[1:0]

PDB

1 Reserved

2

Power Down 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDIB PDRB

3 RF1 N Divider

4 RF2 N Divider 0

5 IF N Divider 0 0

6 Reserved

NRF1[17:0]

NRF[16:0]

NIF[15:0]

.

.

.

15 Reserved

Note: Registers 1 and 6–15 are reserved. Writes to these registers may result in unpredictable behavior. Any register not listed

here is reserved and should not be written.

20

Rev. 1.1

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