Si4133
Control Registers
Table 12. Register Summary
Register Name
Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Main
0 0 0 0 AUXSEL IFDIV 0 0 0 0 LPWR 0 AUTO AUTO RF 0
Configuration
[1:0]
[1:0]
PDB KP PWR
1 Phase
0 0 0 0 0 0 0 0 0 0 0 0 KPI[1:0] KP2[1:0] KP1[1:0]
Detector Gain
2 Power Down 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDIB PDRB
3 RF1
N-Divider
4 RF2
0
N-Divider
5 IF N-Divider 0 0
6 RF1
R-Divider
000 0 0
7 RF2
R-Divider
000 0 0
8 IF R-Divider 0 0 0 0 0
9 Reserved
NRF1[17:0]
NRF2[16:0]
NIF[15:0]
RRF1[12:0]
RRF2[12:0]
RIF[12:0]
.
.
.
15 Reserved
Note: Registers 9–15 are reserved. Writes to these registers may result in unpredictable behavior. Any register not listed here
is reserved and should not be written.
Rev. 1.1
21