SG6741 Ver la hoja de datos (PDF) - Fairchild Semiconductor

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Fabricante

SG6741

Highly Integrated Green-Mode PWM Controller

Fairchild Semiconductor 

Marking Information

SG6741TP

XXXXXXXXYWWV

T: S = SOP

P: Z =Lead Free

Null=regular package

XXXXXXXX: Wafer Lot

Y: Year; WW: Week

V: Assembly Location

Marking for SG6741SZ

ZXYTT

6741

TPM

Marking for SG6741SY

F: Fairchild logo

Z: Plant code

X: 1 digit year code

Y: 1 digit week code

TT: 2 digits die run code

T: Package type (S = SOP)

P: Y=Green package

M: Manufacture flow code

Figure 3. Top Mark

Pin Configuration

GND

FB

GATE

VDD

NC

SENSE

HV

RI

Figure 4. Pin Configuration (Top View)

Pin Definitions

Pin #

1

2

3

4

5

6

7

8

Name

GND

FB

NC

HV

RI

SENSE

VDD

GATE

Description

Ground.

The signal from the external compensation circuit is fed into this pin. The PWM duty cycle is

determined in response to the signal on this pin and the current-sense signal on the SENSE pin.

No connection.

For startup, this pin is pulled high to the line input or bulk capacitor via resistors.

A resistor connected from the RI pin to GND pin provides the SG6741 with a constant current

source. This determines the center PWM frequency. Increasing the resistance reduces PWM

frequency. Using a 26KΩ resistor (RI) results in a 65kHz center PWM frequency.

Current sense. The sensed voltage is used for peak-current-mode control and cycle-by-cycle

current limiting.

Power supply. The internal protection circuit disables PWM output as long as VDD exceeds the

OVP trigger point.

The totem-pole output driver. Soft driving waveform is implemented for improved EMI.

© 2008 Fairchild Semiconductor Corporation

SG6741 • Rev. 1.3.3

3

www.fairchildsemi.com

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