MU9C1480A Ver la hoja de datos (PDF) - Music Semiconductors

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MU9C1480A

MU9C1480A/L LANCAMs®

Music Semiconductors 

MU9C1480A/L Draft

INSTRUCTION SET SUMMARY Continued

CYCLE

LENGTH Command write

CYCLE TYPE

Command Read

Data Write

Data Read

Short

Medium

Long

MOV reg, reg (except L-70)

TCO reg (except CT)

TCO CT (non-reset, HMA invalid)

SPS, SPD, SFR

SBR, RSC

NOP (except L-70)

SFT (A)

MOV reg, mem

Status register or

MOV reg, reg (L-70)

16-bit register

TCO CT (reset)

VBC (NFA invalid)

SFT (L)

NOP (L-70)

MOV mem, reg

TCO CT (non-reset, HMA valid)

CMP

SFF

VBC (NFA valid)

Comparand register

(not last segment)

Mask register

(not last segment)

Memory array

(NFA invalid)

Comparand register

Mask register

Memory array

(NFA valid)

Comparand register

(last segment)

Mask register

(last segment)

Memory array

Note: The specific timing requirements for Short, Medium, and Long cycles are given in the Switching Characteristics section under the

tELEH parameter. For two cycle Command Writes (TCO reg or any instruction with “aaaH” as the source or destination), the

first cycle is short, and the second cycle will be the length given.

Table 7: Instruction Cycle Lengths

REGISTER BIT ASSIGNMENTS

15 14

13 12 11 10

9

RST Match Flag Full Flag Translation

87 6

CAM/RAM Part.

5

43

2

Comp. Mask AR Inc/Dec

1

0

Mode

R

Enable

Enable

Input Not 64 CAM/0 RAM = 000 None = 00 Increment Standard

E

=00

= 00

Translated 48 CAM/16 RAM = 001 MR1 = 01

= 00

= 00

S

Disable

Disable

= 00

32 CAM/32 RAM = 010 MR2 = 10 Decrement Enhanced

E

= 01

= 01

Input

16 CAM/48 RAM = 011 No Change

= 01

= 01

T No Change No Change Translated 48 RAM/16 CAM = 100

= 11

Disable

Reserved

=

= 11

= 11

= 01

32 RAM/32 CAM = 101

= 10

= 10

0

No Change 16 RAM/48 CAM = 110

No Change No Change

= 11

No Change = 111

= 11

= 11

Note: D15 reads back as 0.

Table 8: Control Register Bit Assignments

21

Rev. 3.0 Draft

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