SDA9257 Ver la hoja de datos (PDF) - Siemens AG

Número de pieza

componentes Descripción

Fabricante

SDA9257

Clock Sync Generator

Siemens AG 

SDA 9257

Transmitter Format:

S

Slave Address

1A

Status Byte

AP

N: no acknowledge

Status Byte

KOI

THREUM FFGF

Status Bits

FF

HB

POR

POR

POR

Absolute Difference in Time between the

Horizontal Sync Pulse in CVBS and the HPLL

Greater than or equal to 2.4 µs

Less than 2.4 µs

Status Bit KOI

0

1

Absolute Difference in Time between the

Horizontal Sync Pulse in CVBS and the HPLL

Greater than 0.6 µs

Less than 0.6 µs for 8 or more successive lines

(i.e. HPLL well locked in)

Status Bit THRELIM

0

1

Identified Number of Lines per Field

(refer also to timing diagram 9)

Less than 287

Greater than or equal 287

Between 262 and 264

Between 312 and 314

Between 250 and 275

Between 300 and 325

Status Bits

FFGF

FF

0

1

0

0

1

1

1

0

1

1

1

0

Control Bit

VWW

×

×

1

1

0

0

Field Detection (Applicable to Interlace Only)

First field

Second field

Status Bit HB

0

1

Status bit POR: POR is set by power on reset or by setting the bit RSTH.

POR is reset after reading the status byte.

Semiconductor Group

196

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