SDA 5273 / 75
SDA 5273-2 / 75-2
a) Line Sync Pulse
b) Equalizing Pulse 0 4.7
64
t [ µs]
c) Main Pulse
0 2.35
32 34.35
64
t [ µs]
0
27.3 32
Timing with Tolerances ± 100 ns
59.3 64
t [ µs]
VCS
622 623 624 625
1
2
3
4
5
6
(309) (310) (311) (312)
VCS
310 311 312 313 314 315 316 317 318 319
Interlaced
TCS
622 623 624 625
1
2
3
4
5
6
(309) (310) (311) (312)
TCS
Interlaced
310 311 312 313 314 315 316 317 318 319
(1) (2) (3) (4) (5) (6)
Non-
TCS
Interlaced
309 310 311 312
1
2
3
4
5
6
-312/312 Lines
(310) (311) (312) (313) (1) (2) (3) (4) (5) (6) -313/312 Lines
(621) (622) (623) (624)
-626/624 Lines
(623) (624) (625) (626)
UED04865
Timing Diagram 5a
VCS and TCS in PAL Freerun Mode
Semiconductor Group
26
1997-09-01