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SC68C2550BIB48

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs and 68 mode µP interface

NXP Semiconductors. 

NXP Semiconductors

SC68C2550B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs

Table 2.

Symbol

D0

D1

D2

D3

D4

D5

D6

D7

DSRA

DSRB

DTRA

DTRB

GND

IRQ

OP2A

OP2B

R/W

RESET

RIA

RIB

RTSA

RTSB

RXA

RXB

Pin description …continued

Pin

Type Description

44

I/O Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for transferring

45

I/O

information to or from the controlling CPU. D0 is the least significant bit and the first data bit

in a transmit or receive serial data stream.

46

I/O

47

I/O

48

I/O

1

I/O

2

I/O

3

I/O

39

I

20

I

Data Set Ready (active LOW). These inputs are associated with individual UART channels,

A through B. A logic 0 on this pin indicates the modem or data set is powered-on and is

ready for data exchange with the UART. This pin has no effect on the UART’s transmit or

receive operation.

34

O

Data Terminal Ready (active LOW). These outputs are associated with individual UART

35

O

channels, A through B. A logic 0 on this pin indicates that the SC68C2550B is powered-on

and ready. This pin can be controlled via the modem control register. Writing a logic 1 to

MCR[0] will set the DTRn output pin to logic 0, enabling the modem. This pin will be a logic 1

after writing a logic 0 to MCR[0], or after a reset. This pin has no effect on the UART’s

transmit or receive operation.

17, 24 I

Signal and power ground.

30

O

Interrupt Request. Interrupts from UART channels A-B are wire-ORed internally to function

as a single IRQ interrupt. This pin transitions to a logic 0 (if enabled by the interrupt enable

register) whenever a UART channel(s) requires service. Individual channel interrupt status

can be determined by addressing each channel through its associated internal register,

using CS and A3. An external pull-up resistor must be connected between this pin and VCC.

32

O

Output 2 (user-defined). This function is associated with individual channels A and B. The

9

O

state of these pins is defined by the user through the software settings of MCR[3].

OP2A/OP2B is a logic 0 when MCR[3] is set to a logic 1. OP2A/OP2B is a logic 1 when

MCR[3] is set to a logic 0. The output of these two pins is HIGH after reset.

15

I

A logic LOW on this pin will transfer the contents of the data bus (D[7:0]) from an external

CPU to an internal register that is defined by address bits A[2:0]. A logic HIGH on this pin

will load the contents of an internal register defined by address bits A[2:0] on the

SC68C2550B data bus (D[7:0]) for access by an external CPU.

36

I

Reset (active LOW). A logic 0 on this pin will reset the internal registers and all the outputs.

The UART transmitter output and the receiver input will be disabled during reset time. (See

Section 7.10 “SC68C2550B external reset condition” for initialization details.)

41

I

21

I

Ring Indicator (active LOW). These inputs are associated with individual UART channels,

A through B. A logic 0 on this pin indicates the modem has received a ringing signal from the

telephone line. A logic 1 transition on this input pin will generate an interrupt.

33

O

Request to Send (active LOW). These outputs are associated with individual UART

22

O

channels, A through B. A logic 0 on the RTSn pin indicates the transmitter has data ready

and waiting to send. Writing a logic 1 in the modem control register MCR[1] will set this pin

to a logic 0, indicating data is available. After a reset this pin will be set to a logic 1. This pin

has no effect on the UART’s transmit or receive operation.

5

I

Receive data A, B. These inputs are associated with individual serial channel data to the

4

I

SC68C2550B receive input circuits, A-B. The RXn signal will be a logic 1 during reset, idle

(no data), or when the transmitter is disabled. During the local Loopback mode, the RXn

input pin is disabled and transmit data is connected to the UART receive input, internally.

SC68C2550B_3

Product data sheet

Rev. 03 — 9 October 2009

© NXP B.V. 2009. All rights reserved.

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