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SC68C2550BIB48
NXP Semiconductors.
SC68C2550BIB48 Datasheet PDF : 36 Pages
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NXP Semiconductors
SC68C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
XTAL1
XTAL2
X1
1.8432 MHz
C1
22 pF
C2
33 pF
002aab325
Fig 3. Crystal oscillator connection
Table 6. Baud rate generator programming table using a 1.8432 MHz clock
Output
baud rate
Output
16× clock divisor
(decimal)
Output
16× clock divisor
(HEX)
DLM
program value
(HEX)
DLL
program value
(HEX)
50
2304
900
09
00
75
1536
600
06
00
110
1047
417
04
17
150
768
300
03
00
300
384
180
01
80
600
192
C0
00
C0
1200
96
60
00
60
2400
48
30
00
30
3600
32
20
00
20
4800
24
18
00
18
7200
16
10
00
10
9600
12
0C
00
0C
19.2 k
6
06
00
06
38.4 k
3
03
00
03
57.6 k
2
02
00
02
115.2 k
1
01
00
01
6.6 DMA operation
The SC68C2550B FIFO trigger level provides additional flexibility to the user for block
mode operation. LSR[6:5] provide an indication when the transmitter is empty or has an
empty location(s). The user can optionally operate the transmit and receive FIFOs in the
DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled and the DMA
mode is de-activated (DMA Mode 0), the SC68C2550B activates the interrupt output pin
for each data transmit or receive operation. When DMA mode is activated (DMA Mode 1),
the user takes the advantage of block mode operation by loading or unloading the FIFO in
a block sequence determined by the receive trigger level and the transmit FIFO. In this
mode, the SC68C2550B sets the TXRDYn (or RXRDYn) output pin when characters in the
transmit FIFO is below 16, or the characters in the receive FIFOs are above the receive
trigger level.
SC68C2550B_3
Product data sheet
Rev. 03 — 9 October 2009
© NXP B.V. 2009. All rights reserved.
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