SC68C94 Ver la hoja de datos (PDF) - Philips Electronics
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SC68C94 Datasheet PDF : 33 Pages
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Philips Semiconductors
Quad universal asynchronous receiver/transmitter (QUART)
Product specification
SC68C94
4. Global Transmit Holding Register
The first two Global “registers” are provided by Current Interrupt
Register fields as shown in Figure 5. The interrupting channel
number latched in CIR modifies address decoding so that the
Receive or Transmit Holding Register for the interrupting channel is
accessed during I/O involving the Global Receive and Transmit
Holding Registers. Similarly, for data interrupts from the transmitter
and receiver, the number of characters available for transfer to the
CPU or the number of transmit FIFO positions open is available by
reading the Global Interrupt Byte Count Register. For non-data
interrupts, a read of the Global Interrupt Byte Count Register yields
a value equal to the highest programmable filed.
In effect, once latched by an IACK or the Update CIR command, the
winning interrupt channel number determines the contents of the
global registers. All Global registers will provide data from the
interrupting UART channel.
Interrupt Threshold Calculation
The state of IRQN is determined by comparison of the winning “bid”
value to the Interrupt Threshold field of the Interrupt Control
Register.
The logic of the bidding circuit is such that when no interrupt source
has a value greater than the interrupt threshold then the interrupt is
not asserted and the CIR (Current Interrupt Register) is set to all
ones. When one or more of the 18 interrupt sources which are
enabled via the IMR (Interrupt Mask Register) exceed the threshold
then the interrupt threshold is effectively disconnected from the
bidding operation while the 18 sources now bid against each other.
The final result is that the highest bidding source will disable all
others and its value will be loaded to the CIR and the IRQN pin
asserted low. This all occurs during each cycle of the X1, X2 crystal
clock.
Table 2. Receiver FIFO Interrupt Fill Level
MR0[6]
0
0
1
1
MR1[6]
0
1
0
1
Interrupt Condition
1 or more bytes in FIFO (Rx RDY) default*
3 or more bytes in FIFO
6 or more bytes in FIFO
8 bytes in FIFO (Rx FULL)
For the receiver these bits control the number of FIFO positions
empty when the receiver will attempt to interrupt. After the reset the
receiver FIFO is empty. The default setting of these bits cause the
receiver to attempt to interrupt when it has one or more bytes in it.
Table 3. Receiver FIFO Interrupt Fill Level
MR0[5]
0
0
1
1
MR0[4]
0
1
0
1
Interrupt Condition
8 bytes empty (Tx EMPTY) default*
4 or more bytes empty
6 or more bytes empty
1 or more bytes empty (Tx RDY)
For the transmitter these bits control the number of FIFO positions
empty when the receiver will attempt to interrupt. After the reset the
transmit FIFO has 8 bytes empty. It will then attempt to interrupt as
soon as the transmitter is enabled. The default setting of the MR0
bits (00) condition the transmitter to attempt to interrupt only when it
is competely empty. As soon as one byte is loaded, it is no longer
empty and hence will withdraw its interrupt request.
INTERRUPT NOTE ON 68C94:
For the receivers and transmitters, the bidding of any particular
unit may be held off unless one of four FIFO fill levels is
attained. This is done by setting the RxINT and TxINT bits in
MR0 and MR1 to non-zero values. This may be used to prevent
a receiver or transmitter from generating an interrupt even
though it is filed above the bid threshold. Although this is not
in agreement with the idea that each enabled interrupt source
bid with equal authority, it does allow the flexibility of giving
particular receiver or transmitters more interrupt importance
than others.
This may be used when the Interrupt Threshold is set at or
above 100000. Note than in this case the transmitter cannot
generate an interrupt. If the interrupt threshold MSBs were set
to 011 and the ‘Receiver Interrupt Bits’ on the MR registers set
to a value other than 00 then the RxFIFO could not generate
and interrupt until it had 4, 6 or 8 bytes. This in effect partially
defeats the hardwired characteristic that the receiver interrupts
should have more importance than the transmitter. This
characteristic has been implemented by setting the MSB of the
transmitter bid to zero.
Vectored Interrupts
The QUART responds to an Interrupt Acknowledge (IACK) initiated
by the host by providing an Interrupt Acknowledge Vector on D7:0.
The interrupt acknowledge cycle is terminated with a DACKN pulse.
The vector provided by the QUART can have one of the three forms
under control of the IVC control field (bits 1:0 of the Interrupt Control
Register):
With IVC = 00 (IVR only)
IVR7:0
8
With IVC = 01 (channel number)
IVR7:2
6
With IVC = 10 (type & channel number)
IVR7:5
3
Type
3
Chan #
2
Chan #
2
SD00163
A code of 11 in the Interrupt Vector Control Field of the ICR results
in NO interrupt vector being generated. The external data bus is
driven to a high impedance throughout the IACK cycle. A DACKN
will be generated normally for the IACK cycle, however.
NOTE: If IACKN is not being used then the command “UPDATE
CIR” must be issued for the global and interrupt registers to be
updated.
PROGRAMMING UART CONTROL REGISTERS
The operation of the QUART is programmed by writing control
words into the appropriate registers. Operational feedback is
provided via status registers which can be read by the CPU.
Addressing of the registers is described in Table 1.
The bit formats of the QUART registers are depicted in Table 2.
1995 May 1
11
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