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SC41343D

Encoder and Decoder Pairs CMOS

Freescale Semiconductor 

MC145027 AND MC145028 TIMING

To verify the MC145027 or MC145028 timing, check the

waveforms on C1 (Pin 7) and R2/C2 (Pin 10) as compared to

the incoming data waveform on Din (Pin 9).

The R–C decay seen on C1 discharges down to 1/3 VDD

before being reset to VDD. This point of reset (labelled “DOS”

in Figure 15) is the point in time where the decision is made

whether the data seen on Din is a 1 or 0. DOS should not be

too close to the Din data edges or intermittent operation may

occur.

The other timing to be checked on the MC145027 and

MC145028 is on R2/C2 (see Figure 16). The R–C decay is

continually reset to VDD as data is being transmitted. Only

between words and after the end–of–transmission (EOT)

does R2/C2 decay significantly from VDD. R2/C2 can be used

to identify the internal end–of–word (EOW) timing edge which

is generated when R2/C2 decays to 2/3 VDD. The internal

EOT timing edge occurs when R2/C2 decays to 1/3 VDD.

When the waveform is being observed, the R–C decay

should go down between the 2/3 and 1/3 VDD levels, but not

too close to either level before data transmission on Din re-

sumes.

Verification of the timing described above should ensure a

good match between the MC145026 transmitter and the

MC145027 and MC145028 receivers.

VDD

Din

0V

VDD

C1 2/3

1/3

0V

DOS

DOS

Figure 15. R–C Decay on Pin 7 (C1)

VDD

2/3

R2/C2 1/3

0V

EOW

EOT

Figure 16. R–C Decay on Pin 10 (R2/C2)

MC145026•MC145027•MC145028•SC41343•SC41344

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