SAK-XC2765X-104FXXL Ver la hoja de datos (PDF) - Infineon Technologies

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Fabricante

SAK-XC2765X-104FXXL

16-Bit CMOS Single-Chip Microcontrollers

Infineon Technologies 

XC2765X

XC2000 Family Derivatives / Base Line

Electrical Parameters

4.6.6 Synchronous Serial Interface Timing

The following parameters are applicable for a USIC channel operated in SSC mode.

Note: These parameters are not subject to production test but verified by design and/or

characterization.

Note: Operating Conditions apply.

Table 33 SSC Master/Slave Mode Timing for Upper Voltage Range

Parameter

Symbol

Min.

Values

Typ. Max.

Unit Note /

Test Co

ndition

Master Mode Timing

Slave select output SELO active t1 CC tSYS –

1)

ns 2)

to first SCLKOUT transmit edge

-8

Slave select output SELO inactive t2 CC tSYS –

3)

ns

after last SCLKOUT receive edge

-6

Transmit data output valid time t3 CC -6

–

9

ns

Receive data input setup time to t4 SR 31

–

–

ns

SCLKOUT receive edge

Data input DX0 hold time from t5 SR -4

–

–

ns

SCLKOUT receive edge

Slave Mode Timing

Select input DX2 setup to first t10 SR 7

–

–

ns 4)

clock input DX1 transmit edge

Select input DX2 hold after last t11 SR 7

–

–

ns 4)

clock input DX1 receive edge

Data input DX0 setup time to

t12 SR 7

–

–

ns 4)

clock input DX1 receive edge

Data input DX0 hold time from t13 SR 5

–

–

ns 4)

clock input DX1 receive edge

Data output DOUT valid time

t14 CC 7

–

33

ns 4)

1) The maximum value further depends on the settings for the slave select output leading delay.

2) tSYS = 1/fSYS (= 12.5 ns @ 80 MHz)

3) The maximum value depends on the settings for the slave select output trailing delay and for the shift clock

output delay.

4) These input timings are valid for asynchronous input signal handling of slave select input, shift clock input, and

receive data input (bits DXnCR.DSEN = 0).

Data Sheet

111

V2.0, 2009-03

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