SAA7120H Ver la hoja de datos (PDF) - Philips Electronics
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SAA7120H Datasheet PDF : 36 Pages
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Philips Semiconductors
Digital video encoder
Product specification
SAA7120H; SAA7121H
Table 24 Logic levels and function of SRCV1
DATA BYTE
SRCV11
0
0
1
SRCV10
0
1
0
AS OUTPUT AS INPUT
VS
FS
FSEQ
VS
FS
FSEQ
1
1
−
−
FUNCTION
vertical sync each field; default after reset
frame sync (odd/even)
field sequence, vertical sync every fourth field (PAL = 0)
or eighth field (PAL = 1)
not applicable
Table 25 Subaddresses 6CH and 6DH
DATA BYTE
DESCRIPTION
HTRIG
sets the horizontal trigger phase related to signal on RCV1 or RCV2 input
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; increasing HTRIG decreases
delays of all internally generated timing signals; reference mark: analog output horizontal sync
(leading slope) coincides with active edge of RCV used for triggering at HTRIG = 398H (398H)
Table 26 Subaddress 6DH
DATA BYTE
DESCRIPTION
VTRIG
sets the vertical trigger phase related to signal on RCV1 input
increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines;
variation range of VTRIG = 0 to 31 (1FH)
Table 27 Subaddress 6EH
DATA BYTE
SBLBN
PHRES
FLC
LOGIC
LEVEL
0
1
−
−
DESCRIPTION
vertical blanking is defined by programming of FAL and LAL; default after reset
vertical blanking is forced in accordance with “CCIR 624” (50 Hz) or RS170A (60 Hz)
selects the phase reset mode of the colour subcarrier generator; see Table 28
field length control; see Table 29
Table 28 Logic levels and function of PHRES
DATA BYTE
PHRES1
0
0
1
1
PHRES0
0
1
0
1
DESCRIPTION
no reset or reset via RTCI from SAA7111 if bit RTCE = 1; default after reset
reset every two lines
reset every eight fields
reset every four fields
2002 Oct 11
18
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