SAA4700T Ver la hoja de datos (PDF) - Philips Electronics
Número de pieza
componentes Descripción
Fabricante
SAA4700T Datasheet PDF : 14 Pages
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Philips Semiconductors
VPS dataline processor
Preliminary specification
SAA4700T
handbook, full pagewidth
CVBS
4.7 nF
2
470 pF
CSO
0.1
µF
5
6
SYNC
SEPARATOR
SAA4700T line 16
1 nF 1
DATA
data
SLICER
4.7
kΩ
(test line 16)
12
FIELD SELECTOR
LINE 16 DECODER
INPUT
CONTROLLER
DAV
13
OUTPUT
CONTROLLER
5
AD = LOW
8
I2C-BUS
9
SCL
CONTROL 10 SDA
8
40 BIT DATA
REGISTER
data
4
40 BIT
DATA LATCH
CLOCK
REGENERATOR
75 kΩ
VCS
(2%) 15
to VP
PLL WITH
4.7 nF
5 MHz VCO AND
19 PHASE DETECTOR
22
nF
16
TIME BASE
6
MULTIPLEXER
7 n.c.
14 n.c.
20 n.c.
REFERENCE
VOLTAGES
POWER-ON RESET
external
reset
34
17 18
11
8.2 kΩ
clock pulse
Fig.1 Block diagram and test circuit.
0.1 µF
+5 V
VP
MGH128
FUNCTIONAL DESCRIPTION
Dataline 16
The information in dataline 16 consists of fifteen 8-bit
words; the total information content is shown in Table 1;
and the organization of transmitted bytes is shown in
Table 2.
Out of the fifteen possible 8-bit words the SAA4700T
extracts words 5 and 11 to 14. The contents of these words
can be read via the built-in I2C-bus interface. The circuit is
fully transparent, thus each bit is transferred without
modification with only the sequence of words being
changed. Words 11 to 14 are transmitted first followed by
word 5.
By evaluating the sliced sync signal the circuit can identify
the beginning of dataline 16 in the first field. The dataline
decoder stage releases the start code detector. When a
correct start code is detected (for timing of start code
detection see Fig.3) words 5 and 11 to 14 are decoded,
checked for biphase errors and stored in a register bank. If
no biphase error has occurred, the contents of the register
bank are transferred to a second register bank by the data
valid control signal. If the system has been addressed, this
transfer will be delayed until the next start or stop condition
of the I2C-bus has been received.
The last bit of correct information on the dataline remains
available until it is read via the I2C-bus. Once the stored
information has been read it is considered to be no longer
valid and the internal new data flag is reset. Subsequently,
if the circuit is addressed, the only VPS data that will be
sent back is “FFF to F”. The same conditions apply after
power-up when no data can be read out. New data is
available after reception of another error-free dataline 16.
March 1991
3
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