S6B0086 Ver la hoja de datos (PDF) - Samsung

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S6B0086

80 CH SEGMENT / COMMON DRIVER FOR DOT MATRIX LCD

Samsung 

80CH COMMON / SEGMENT DRIVER FOR DOT MATRIX LCD

S6B0086

BLOCK DESCRIPTION

Name

Clock control

Data latch

control

Power down

function

Output level

selector

20x4-bit

segment data

I-directional

shift register

80-bit data

latch /

common data

I-directional

shift register

80-bit level

shifter

80-bit 4-level

driver

Function

Generates latch clock (LCK), shift clock (SCK) and control clock timing

according to the input of CL1, CL2 and control inputs (CS, AMS). In common

driver application mode, this block generates the shift clock (LCK) for the

common data Bi-directional shift register.

Determines the direction of segment data shift, and input data of each

Bi-directional shift register. In 4-bit segment data parallel transfer mode, data

is shifted by a 4-bit unit. In common driver application mode, data is

transferred to the common data shift register directly, which disables this

block.

Controls the clock enable state of the current driver according to the input

value of enable pin (ELB or ERB). If enable input value is “Low”, every clock

of the current driver is enabled and the clock control block works. But if

enable input is “High”, current driver is disabled and the input data value has

no effect on the output level. So power consumption can be lowered.

Controls the output voltage level according to the input control pin (M and

DISPOFFB) (refer to PIN DESCRIPTION).

Stores output data value by shifting the input values. In 1-bit serial interface

mode application, all 80 shift clocks (SCK) are needed to store all the display

data. But in 4-bit parallel transfer mode application, only 20 clocks are

needed. In common driver application mode, this block does not work.

In segment driver application mode, the data from the 20x4-bit segment data

shift register are latched for segment driver output. In single-type common

driver application,1-bit input data (from DL or DR pin) is shifted and latched

by the direction according to the SHL signal input. In dual-type common

application mode, 80-bit registers are divided by two blocks and controlled

independently (refer to NOTE 3).

Voltage level shifter block for high voltage part. The inputs of this block are of

logical voltage level and the outputs of this block are at high voltage level

value. These values are input in to the driver.

Selects the output voltage level according to M and latched data value. If the

data value is "High" the driver output is at selected voltage level (V0 or V5),

and in the reverse case the driver output value is at the non-selected level

(V12 or V43). In segment driver application mode, non-selected output value

is V2 or V3. and when in common driver application, this value becomes V1

or V4.

COM / SEG

COM / SEG

SEG

SEG

COM / SEG

SEG

COM / SEG

SEG

SEG

7

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