S3C2440X Ver la hoja de datos (PDF) - Samsung

Número de pieza

componentes Descripción

Fabricante

S3C2440X

32-bit RISC microprocessor.

Samsung 

S3C2440X

2003.10.15

PRODUCT OVERVIEW

SIGNAL DESCRIPTIONS

Table 1-3. S3C2440X Signal Descriptions (Sheet 1 of 6)

Signal

Bus Controller

OM[1:0]

ADDR[26:0]

DATA[31:0]

nGCS[7:0]

nWE

nOE

nXBREQ

nXBACK

nWAIT

SDRAM/SRAM

nSRAS

nSCAS

nSCS[1:0]

DQM[3:0]

SCLK[1:0]

SCKE

nBE[3:0]

nWBE[3:0]

NAND Flash

CLE

ALE

nFCE

nFRE

nFWE

NCON

FRnB

I/O

Descriptions

I OM[1:0] sets S3C2440X in the TEST mode, which is used only at fabrication. Also, it

determines the bus width of nGCS0. The pull-up/down resistor determines the logic

level during RESET cycle.

00:Nand-boot 01:16-bit

10:32-bit

11:Test mode

O ADDR[26:0] (Address Bus) outputs the memory address of the corresponding bank .

IO DATA[31:0] (Data Bus) inputs data during memory read and outputs data during

memory write. The bus width is programmable among 8/16/32-bit.

O nGCS[7:0] (General Chip Select) are activated when the address of a memory is

within the address region of each bank. The number of access cycles and the bank

size can be programmed.

O nWE (Write Enable) indicates that the current bus cycle is a write cycle.

O nOE (Output Enable) indicates that the current bus cycle is a read cycle.

I nXBREQ (Bus Hold Request) allows another bus master to request control of the

local bus. BACK active indicates that bus control has been granted.

O nXBACK (Bus Hold Acknowledge) indicates that the S3C2440X has surrendered

control of the local bus to another bus master.

I nWAIT requests to prolong a current bus cycle. As long as nWAIT is L, the current

bus cycle cannot be completed.

O SDRAM Row Address Strobe

O SDRAM Column Address Strobe

O SDRAM Chip Select

O SDRAM Data Mask

O SDRAM Clock

O SDRAM Clock Enable

O Upper Byte/Lower Byte Enable(In case of 16-bit SRAM)

O Write Byte Enable

O Command Latch Enable

O Address Latch Enable

O Nand Flash Chip Enable

O Nand Flash Read Enable

O Nand Flash Write Enable

I Nand Flash Configuration

I Nand Flash Ready/Busy

* If NAND flash controller isn’t used, it has to be

pull-up. (3.3V)

Preliminary product information describes products that are in development,

for which full characterization data and associated errata are not yet available

Specifications and information herein are subject to change without notice.

1-21

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