SDU13A3-0C Ver la hoja de datos (PDF) - Seiko Epson Corp

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componentes Descripción

Fabricante

SDU13A3-0C

LCD Controller ICs

Seiko Epson Corp 

PIN DESCRIPTION

Pin Name

A0

8080 family interface

A0

RD

WR

0

0

1

1

0

1

0

1

0

1

1

0

Function

Function

Status flag read

Display data and cursor address read

Display data and parameter write

Command write

6800 family interface

A0

R/W

E

0

1

1

1

1

1

0

0

1

1

0

1

Function

Status flag read

Display data and cursor address read

Display data and parameter write

Command write

RD or E

WR or R/W

CS

RES

When the 8080 family interface is selected, this signal acts as the active-LOW read strobe. The

S1D13305 series output buffers are enabled when this signal is active.

When the 6800 family interface is selected, this signal acts as the active-HIGH enable clock.

Data is read from or written to the S1D13305 series when this clock goes HIGH.

When the 8080 family interface is selected, this signal acts as the active-LOW write strobe. The

bus data is latched on the rising edge of this signal.

When the 6800 family interface is selected, this signal acts as the read/write control signal. Data

is read from the S1D13305 series if this signal is HIGH, and written to the S1D13305 series if

it is LOW.

Chip select. This active-LOW input enables the S1D13305 series. It is usually connected

to the output of an address decoder device that maps the S1D13305 series into the memory

space of the controlling microprocessor.

This active-LOW input performs a hardware reset on the S1D13305 series. It is a

Schmitt-trigger input for enhanced noise immunity; however, care should be taken to ensure

that it is not triggered if the supply voltage is lowered.

5.2.4. Display memory control

The S1D13305 series can directly access static RAM and

PROM. The designer may use a mixture of these two

types of memory to achieve an optimum trade-off be-

tween low cost and low power consumption.

Pin Name

Function

VA0 to VA15

16-bit display memory address. When accessing character generator RAM or ROM, VA0 to

VA3, reflect the lower 4 bits of the S1D13305 series’s row counter.

VD0 to VD7 8-bit tristate display memory data bus. These pins are enabled when VR/W is LOW.

VWR

Active-LOW display memory write control output.

VRD

Active-LOW display memory read control output.

VCE

Active-LOW static memory standby control signal. VCE can be used with CS.

6

EPSON

S1D13305 Series

Technical Manual

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