S1D13705F00A Ver la hoja de datos (PDF) - Seiko Epson Corp

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componentes Descripción

Fabricante

S1D13705F00A

Embedded Memory LCD Controller

Seiko Epson Corp 

Epson Research and Development

Vancouver Design Center

4 Functional Block Diagram

Register

Generic MPU

MC68K

SH-3

SH-4

Host

I/F

40k x 16-bit SRAM

Memory

Controller

Power Save

Clocks

Look-Up

Table

LCD

I/F

Page 15

LCD

Bus Clock

Memory Clock

Sequence Controller

Pixel Clock

Figure 4-1: System Block Diagram Showing Data Paths

4.1 Functional Block Descriptions

4.1.1 Host Interface

The Host Interface provides the means for the CPU/MPU to communicate with the display

buffer and internal registers.

4.1.2 Memory Controller

The Memory Controller arbitrates between CPU accesses and display refresh accesses. It

also generates the necessary signals to control the SRAM frame buffer.

4.1.3 Sequence Controller

The Sequence Controller controls data flow from the Memory Controller through the Look-

Up Table and to the LCD Interface. It also generates memory addresses for display refresh

accesses.

Hardware Functional Specification

Issue Date: 02/02/01

S1D13705

X27A-A-001-10

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