RTL8181 Ver la hoja de datos (PDF) - Realtek Semiconductor
Número de pieza
componentes Descripción
Fabricante
RTL8181 Datasheet PDF : 50 Pages
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PAPE O 82
PE1/PHIT O 84
XQ
PE2
O 85
RXIP
AI* 110
RXIN
RXQP
X 109
AI 106
RXQN
RSSI
TXDET
VREFI
TXIP
X 105
X 103
AI 102
AI 101
AO 97
TXIN AO 96
TXQP AO 94
TXQN AO 93
TXAGC AO 91
RXAGC AO 90
Miscellaneous
R10K I/O 99
XO
O 87
XI
I 88
PCI Interface
AD31-0 T/S *X
C/BE3-0 T/S *X
CLK
O *X
DEVSELB S/T/ *X
S
FRAMEB S/T/ *X
S
GNTB
REQB
IDSEL
INTAB
IRDYB
T/S *X
T/S *X
O *X
O/D *X
S/T/ *X
S
CONFIDENTIAL
RTL8181
K19
Transmit PA Power Enable: Assert high when starting transmission.
K18
Not used in the Maxim RF chipset.
J20
Not used in the Maxim RF chipset now.
B19
Receive (Rx) In-phase Analog Data: Positive path of differential pair.
B20
Receive (Rx) In-phase Analog Data: Negative path of differential pair.
C18
Receive (Rx) Quadrature-phase Analog Data: Positive path of differential pair.
C19
Receive (Rx) Quadrature-phase Analog Data: negative path of differential pair.
D17
Not used in Maxim RF chipset.
D18
To internal ADC which detects transmit power.
C20
Not used in Maxim RF chipset.
E19
Transmit (TX) In-phase Digital Data:Combining before connecting to TX_I of
F18
RF2948B.
E20
Transmit (TX) Quadrature Digital Data: Combining before connecting to TX_Q
F20
of RF2948B.
F19
Transmit gain control output to RF2948.
G18
Analog Drive to the Receive r AGC Control.
E18
This pin must be pulled low by a 10K O resistor.
H18
Crystal Feedback Output: This output is reserved for crystal connection. It should
be left open when XI is driven with an external 44 MHz oscillator.
H19
44 MHz OSC Input
A13,B12,A8 PCI address and data multiplexed pins. The address phase is the first clock cycle in
,C8,B8,C4, which FRAMEB is asserted. During the address phase, AD31-0 contains a physical
B3,A3,C2,D address (32 bits). For I/O, this is a byte address, and for configuration and memory, it
3,C1,G1,H3, is a double-word address. Write data is stable and valid when IRDYB is asserted. Read
J3,V2,V1,V data is stable and valid when TRDYB is asserted. Data I is transferred during those
3,W2,V4,w clocks where both IRDYB and TRDYB are asserted.
3,Y3,W6,Y
6,V7,Y14,
W14,Y15,Y
19,U16,R18
,T20,R19
W20,V19,U PCI bus command and byte enables multiplexed pins. During the address phase
17,V20 of a transaction, C/BE3-0 define the bus command. During the data phase,
C/BE3-0 are used as Byte Enables. The Byte Enables are valid for the entire data
phase and determine which byte lanes carry meaningful data. C/BE0 applies to
byte 0, and C/BE3 applies to byte 3.
N19
PCI clock: This clock input provides timing for all PCI transactions and is input
to the PCI device.
P3
Device Select: As a bus master, the RTL8181 samples this signal to insure that a
PCI target recognizes the destination address for the data transfer.
N20
Cycle Frame: As a bus master, this pin indicates the beginning and duration of an
access. FRAMEB is asserted low to indicate the start of a bus transaction. While
FRAMEB is asserted, data transfer continues. When FRAMEB is deasserted, the
transaction is in the final data phase.
As a target, the device monitors this signal before decoding the address to check
if the current transaction is addressed to it.
H20
Grant:Grant indicate to the agent that access to the bus has been granted.
J18
Request: Request indicates to the ar biter that this agent desires use of the bus.
A16
Initialization Device Select: This pin is used as a chip select during configuration
read and write transactions..
A17
Interrupt A: Used to request an interrupt. It is asserted low when an interrupt
condition occurs, as defined by the Interrupt Status, Interrupt Mask.
M18
Initiator Ready: This indicates the initiating agent’s ability to complete the
current data phase of the transaction.
As a bus master, this signal will be asserted low when the RTL8181 is ready to
10
v1.0
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