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componentes Descripción

Fabricante

RT9205A

Dual Regulators - Synchronous Buck PWM DC-DC and Linear Controller

Richtek Technology 

RT9205/A

Preliminary

Input / Output Capacitor

High frequency/long life decoupling capacitors should be

placed as close to the power pins of the load as physically

possible. Be careful not to add inductance to the PCB

trace, as it could eliminate the performance from utilizing

these low inductance components. Consult with the

manuf acturer of the load on specific decoupling

requirements.

The output capacitors are necessary for filtering output

and stabilizing the close loop (see the PWM loop stability).

For powering advanced high-speed processors, it is

required to meet fast load transient requirement. Also high

ESR usually induces ripple that may trigger UV or OV

protections. So High frequency capacitors with low ESR/

ESL capacitors are recommended here.

Linear Regulator Driver

The linear controller of RT9205/A was designed to drive an

external bipolar NPN transistor or a N-MOSFET. For a N-

Channel MOSFET, normally DRV need to provide minimum

VOUT2+VT+gate-drive voltage to keep VOUT2 as the set

voltage. When driving MOSFET operating at a 5V power

supply, the gate-drive will be limited at 5V. At this situation,

as shown in Figure 7 a MOSFET with low VT threshold

(VT = 1V) and set Vout2 below 2.5V are suggested. In

VBOOT = 12V operation condition, as Figure 8 shown, VCC

is regulated higher than 6V, which providing higher gate-

drive capability for driving the MOSFET, VOUT2 can be set

as VOUT2 ≤ 3.3V.

VCC = 5V

Max. 5V

Suggest Low

VT MOSFET

VOUT2 < 2.5V

DRV

BOOT

FBL

VCC

RT9205/A

R3

R4 R4<1K

Figure 7

Max. 6V

Suggest Low

VT MOSFET

VOUT2 < 3.3V

VBOOT = 12V

DRV

BOOT

FBL

6V VCC

RT9205/A

R3

R4

R4<1K

Figure 8

PWM Loop Stability

The RT9205/A is a voltage mode buck controller designed

for 5V step-down applications. The gain of error amplifier

is fixed at 35dB for simplifying design.

The output amplitude of ramp oscillator is 1.6V, the loop

gain and loop pole/zero are calculated as follows :

5 0.8

DC loop gain GA = 35 dB × ×

1.75 VOUT

1

LC filter pole PO =

2π LC

Error Amp pole PA = 300kHz

1

ESR zero ZO =

2πESR × C

The RT9205/A Bode plot is as shown in Figure 9. It is

stable in most of application conditions.

VOUT = 3.3V

COUT = 1500uF(33mΩ)

L = 2uH

40

VOUT = 1.5V

VOUT = 2.5V

30 VOUT = 3.3V

PO = 2.9kHz

ZO = 3.2kHz

20

Loop Gain

10

100

1k

10k

100k

1M

Figure 9

www.richtek.com

12

DS9205/A-08 March 2007

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