RT9201 Ver la hoja de datos (PDF) - Richtek Technology

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componentes Descripción

Fabricante

RT9201

High Efficiency PWM Step-Down DC-DC Converter

Richtek Technology 

RT9201

Output Capacitor Selection

The capacitor's ESR determines the output ripple voltage

and the initial voltage drop following a high slew-rate

transient's edge. Typically, if the ESR requirement is

satisfied, the capacitance is adequate to filtering. The

output ripple voltage can be calculated as :

ΔVOUT

=

ΔIC(ESR +

1

8 × COUT

× fOSC

)

The ceramic capacitor with low ESR value provides the

low output ripple and low size profile. Connect a 22µF

ceramic capacitor at output terminal for good performance

and place the input and output capacitors as close as

possible to the device.

Layout Considerations

Follow the PCB layout guidelines for optimal performance

of RT9201.

1. For the main current paths as indicated in bold lines in

Figure 3, keep their traces short and wide.

2. Put the input capacitor as close as possible to the

device pins (PVDD and PGND).

3. LX node is with high frequency voltage swing and

should be kept small area. Keep analog components

away from LX node to prevent stray capacitive noise

pick-up.

4. Connect f eedback network behind the output

capacitors. Keep the loop area small. Place the

feedback components near the RT9201.

5. Connect all analog grounds to a command node and

then connect the command node to the power ground

behind the output capacitors.

6. An example of 2-layer PCB layout is shown in

Figure 4 to Figure 6 for reference.

R3

1 EN

8

PVDD

9 VDD

10 NC RT9201 LX 7

C9

L1

VDD

VOUT

4 NC

5 GND

6

PGND

FB SS 2

3

C4

C7 C6

R2

R1

C1

C2

Figure 3. RT9201 Layout Diagram

www.richtek.com

12

Figure 4. Top Layer

Figure 5. Bottom Layer

Figure 6. Silkscreen Layer

DS9201-12 August 2007

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