RT8286 Ver la hoja de datos (PDF) - Richtek Technology
Número de pieza
componentes Descripción
Fabricante
RT8286 Datasheet PDF : 14 Pages
| |||
RT8286
EMI Consideration
Since parasitic inductance and capacitance effects in PCB
circuitry would cause a spike voltage on SW pin when
high side MOSFET is turned-on/off, this spike voltage on
SW may impact on EMI performance in the system. In
order to enhance EMI performance, there are two methods
to suppress the spike voltage. One way is by placing an
R-C snubber (RS*, CS*) between SW and GND and locating
them as close as possible to the SW pin, as shown in
Figure 5. Another method is by adding a resistor in series
with the bootstrap capacitor, CBOOT, but this method will
decrease the driving capability to the high side MOSFET.
It is strongly recommended to reserve the R-C snubber
during PCB layout for EMI improvement. Moreover,
reducing the SW trace area and keeping the main power
in a small loop will be helpful on EMI performance. For
detailed PCB layout guide, please refer to the section
Layout Considerations.
VIN
1 VIN
BOOT 4
CIN
REN*
RT8286
SW 2, 3
CBOOT
L
5 EN
CS*
CEN*
RS*
R1
7 VCC
FB 6
RT
CC
GND 8, 9 (Exposed Pad)
R2
* : Optional
Figure 5. Reference Circuit with Snubber and Enable Timing Control
VOUT
COUT
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
SOP-8 (Exposed Pad) packages, the thermal resistance,
θJA, is 75°C/W on a standard JEDEC 51-7 four-layer
thermal test board. The maximum power dissipation at
TA = 25°C can be calculated by the following formula :
PD(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W for
SOP-8 (Exposed Pad) package
The maximum power dissipation depends on the operating
ambient temperature for fixed TJ(MAX) and thermal
resistance, θJA. The derating curve in Figure 6 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
1.4
Four-Layer PCB
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 6. Derating Curve of Maximum Power Dissipation
Copyright ©2012 Richtek Technology Corporation. All rights reserved.
www.richtek.com
12
is a registered trademark of Richtek Technology Corporation.
DS8286-02 June 2012
Share Link: 