R5E70835RN80FTV Ver la hoja de datos (PDF) - Renesas Electronics
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R5E70835RN80FTV Datasheet PDF : 1622 Pages
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17.6.4 Note for Reception Operations in SSU Slave Mode ............................................. 899
17.6.5 Note on Master Transmission and Master Reception Operations
in SSU Mode......................................................................................................... 900
17.6.6 Note on DTC Transfers......................................................................................... 900
Section 18 I2C Bus Interface 2 (I2C2) ................................................................901
18.1 Features.............................................................................................................................. 901
18.2 Input/Output Pins ............................................................................................................... 904
18.3 Register Descriptions ......................................................................................................... 905
18.3.1 I2C Bus Control Register 1 (ICCR1) ..................................................................... 905
18.3.2 I2C Bus Control Register 2 (ICCR2) ..................................................................... 908
18.3.3 I2C Bus Mode Register (ICMR)............................................................................ 910
18.3.4 I2C Bus Interrupt Enable Register (ICIER) ........................................................... 912
18.3.5 I2C Bus Status Register (ICSR)............................................................................. 914
18.3.6 I2C Bus Slave Address Register (SAR)................................................................. 917
18.3.7 I2C Bus Transmit Data Register (ICDRT)............................................................. 918
18.3.8 I2C Bus Receive Data Register (ICDRR) .............................................................. 918
18.3.9 I2C Bus Shift Register (ICDRS)............................................................................ 918
18.3.10 NF2CYC Register (NF2CYC) .............................................................................. 919
18.4 Operation ........................................................................................................................... 920
18.4.1 I2C Bus Format...................................................................................................... 920
18.4.2 Master Transmit Operation ................................................................................... 921
18.4.3 Master Receive Operation..................................................................................... 923
18.4.4 Slave Transmit Operation ..................................................................................... 926
18.4.5 Slave Receive Operation....................................................................................... 929
18.4.6 Clock Synchronous Serial Format ........................................................................ 930
18.4.7 Noise Filter ........................................................................................................... 934
18.4.8 Example of Use..................................................................................................... 935
18.5 I2C2 Interrupt Sources........................................................................................................ 939
18.6 Operation Using the DTC .................................................................................................. 940
18.7 Bit Synchronous Circuit..................................................................................................... 941
18.8 Usage Note......................................................................................................................... 942
18.8.1 Module Standby Mode Setting ............................................................................. 942
18.8.2 Issuance of Stop Condition and Repeated Start Condition ................................... 942
18.8.3 Issuance of a Start Condition and Stop Condition in Sequence ............................ 942
18.8.4 Settings for Multi-Master Operation..................................................................... 942
18.8.5 Reading ICDRR in Master Receive Mode............................................................ 943
Section 19 A/D Converter (ADC)......................................................................945
19.1 Features.............................................................................................................................. 945
Rev. 4.00 Dec. 15, 2009 Page xix of lviii
REJ09B0181-0400
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