R2A15908SP Ver la hoja de datos (PDF) - Renesas Electronics
Número de pieza
componentes Descripción
Fabricante
R2A15908SP Datasheet PDF : 14 Pages
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R2A15908SP
Bus Line Timing Specification
tR, tF
VIL
SDA
VIH
VIL
SCL
VIH
tHD: STA
S
tSU: DAT
tHD: DAT
tLOW
tHIGH
tSU: STA
S
tBUF
tSU: STO
P
S
Parameters
Symbol Min
Min input low voltage
VIL
0
Max input high voltage
VIH
3.0
SCL clock frequency
fSCL
—
Time the bus must be free before a new transmission can start
tBUF
4.7
Hold time start condition. After this period the first clock pulse is generated tHDSTA
4.0
The Low period of the clock
tLow
4.7
The High period of the clock
tHigh
4.0
Set-up time for start condition (Only relevant for a repeated start condition) tSU: STA
4.7
Hold time DATA
tHD: DAT
0
Set-up time DATA
tSU: DAT
250
Rise time of both SDA & SCL lines
tR
—
Fall time of both SDA & SCL lines
tF
—
Set-up time for stop condition
tSU: STO
4.0
Max
1.5
5.0
100
—
—
—
—
—
—
—
1000
300
—
Units
V
V
kHz
μs
μs
μs
μs
μs
μs
ns
ns
ns
μs
REJ03F0270-0100 Rev.1.00 Jan 25, 2008
Page 12 of 13
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