E28F008BV-B70 Ver la hoja de datos (PDF) - Intel
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E28F008BV-B70 Datasheet PDF : 58 Pages
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E
8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
4.14 AC Characteristics—CE# Controlled Write Operations(1, 11)—
Extended Temperature
Prod TBE-120
TBV-90
TBV-90
TBE-120
Sym
Parameter
VCC 2.7V–3.6V(9) 3.3±0.3V(9) 5V±10%(10) Unit
Load
50 pF
50 pF
100 pF
Notes Min Max Min Max Min Max
tAVAV
tPHEL
Write Cycle Time
RP# High Recovery to CE#
Going Low
120
120
90
ns
1.5
1.5
0.45
µs
tWLEL
WE# Setup to CE# Going Low
0
0
0
ns
tPHHEH Boot Block Lock Setup to CE#
6,8 200
200
100
ns
Going High
tVPEH
VPP Setup to CE# Going High
5,8 200
200
100
ns
tAVEH
Address Setup to CE# Going
High
90
90
60
ns
tDVEH
Data Setup to CE# Going High
3
70
70
60
ns
tELEH
CE# Pulse Width
4
90
90
60
ns
tEHDX
Data Hold Time from CE# High
0
0
0
ns
tEHAX
Address Hold Time from CE#
4
0
0
0
ns
High
tEHWH
WE# Hold Time from CE# High
3
0
0
0
ns
tEHEL
CE# Pulse Width High
20
20
20
ns
tEHQV1 Duration of Word/Byte Write
2,5
6
6
6
µs
Operation
tEHQV2 Duration of Erase Operation
2,5,6 0.3
0.3
0.3
s
(Boot)
tEHQV3 Duration of Erase Operation
2,5 0.3
0.3
0.3
s
(Parameter)
tEHQV4 Duration of Erase Operation
2,5 0.6
0.6
0.6
s
(Main)
tQVVL
VPP Hold from Valid SRD
5,8
0
0
0
ns
tQVPH
RP# VHH Hold from Valid SRD
6,8
0
0
0
ns
tPHBR
Boot-Block Lock Delay
7,8
200
200
100 ns
NOTES:
See AC Characteristics—WE# Controlled Write Operations for notes 1 through 10.
11. Chip-Enable controlled writes: write operations are driven by the valid combination of CE# and WE# in systems where CE#
defines the write pulse-width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times should be
measured relative to the CE# waveform.
SEE NEW DESIGN RECOMMENDATIONS
55
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