PEB20324 Ver la hoja de datos (PDF) - Infineon Technologies

Número de pieza

componentes Descripción

Fabricante

PEB20324

Multichannel Network Interface Controller for HDLC + Extensions MUNICH128X

Infineon Technologies 

PEB 20324

PEF 20324

Pin Descriptions

Table 2-3

Pin No.

96

94

95

90

92

91

93

Pin Descriptions by Functional Block: Port 2 Serial Interface

Symbol Type Description

RxCLK2 I

Receive Clock 2

The clock input pin used for sampling the data on

RxD2. The MUNICH128X supports the following PCM

clock rates, programmed via the MODE1 register:

T1: 1.536 MHz, 1.544 MHz, 3.088 MHz, 6.176 MHz;

E1: 2.048 MHz, 4.096 MHz, 8.192 MHz.

RxD2

I

Receive Data 2

The data input pin which is sampled using RxCLK2.

RSP2

I

Receive Synchronization Pulse 2

The input pin used for Rx PCM frame synchronization;

the synchronization pulse marks the first bit in the

PCM frame.

TxCLK2 I

Transmit Clock 2

The clock input used for clocking out the data on

TxD2. In most applications, the signal that drives this

pin is externally connected to RxCLK2.

TxD2

O Transmit Data 2

Provides the data which is clocked out of the

MUNICH128X by TxCLK2; data is push-pull for active

bits in the PCM frame and TRISTATE™ for inactive

bits.

TSP2

I

Transmit Synchronization Pulse 2

The input pin used for Tx PCM frame synchronization;

the synchronization pulse marks the last bit in the

PCM frame.

TxDEN2 O

Transmit Data Enable 2

An active low output signal which specifies data on the

TxD2 output pin is valid.

Hardware Reference Manual

19

04.99

Share Link: