PEB2035 Ver la hoja de datos (PDF) - Siemens AG

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componentes Descripción

Fabricante

PEB2035

Advanced CMOS Frame Aligner ACFA

Siemens AG 

PEB 2035

1.3 Pin Definitions and Functions (cont’d)

P-LCC

Pin No.

34

P-DIP Symbol

Pin No.

30

XDI

Input (I)

Output (O)

I

35

31

RESQ

I

36

32

ACKNLQ / I

XSIG

Function

Transmit Data In

Transmit data received from the system internal

highway with 4096 kbit/s or 2048 kbit/s (bit

MODE.IMOD). Latching of data is done with

negative transitions of SCLK. The delay between

the beginning of time-slot 0 and the initial edge of

SCLK (after SYPQ goes active) is determined by

the values of transmit time-slot offset

XC1.XTO5 … 0 and transmit clock-slot offset

XC0 . XCO2 … 0. Additionally, for PCM 24 the

channel/time-slot correspondence between route

and system side is selected via bit MODE.CTM.

Reset (active low)

A low signal will initialize all internal flip flops. The

ACFA is switched to PCM 30 mode. All output

stages are tristated while RESQ is active.

DMA Acknowledge (active low)

If access to internal signaling stacks is enabled via

bit XCO.ISIG this input acts as an 'access enable'

to the internal stacks RSIG and XSIG in

conjunction with a read/write command without the

need of generating the chip enable signal CEQ. In

this case it should be connected to the

acknowledge output of the DMA controller to

enable IO-to-memory transfers.

PCM 30

No function if XCO.ISIG is set to '0'. In that case

this input has to be fixed either to VDD or to VSS.

PCM 24: Transmit Signaling Data

If XCO.ISIG is set to '0' the external signaling

mode is enabled. This port acts as input for the

signaling data requested by the marker XSIGM.

Latching of data is done with negative transitions

of SCLK. If not used port XSIG should be tied to

port XDI.

Semiconductor Group

15

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