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componentes Descripción

Fabricante

PDIUSBD12

USB interface device with parallel bus

Philips Electronics 

Philips Semiconductors

PDIUSBD12

USB interface device with parallel bus

DMREQ

tRHSH

tAHRH

DMACK_N

RD_N/WR_N

EOT_N (1)

tSHAH

tEL

EOT_N is considered valid when DMACK_N, RD_N/WR_N and EOT_N are all LOW.

Fig 19. Single-cycle DMA timing.

DMREQ

DMACK_N

RD_N/WR_N

Fig 20. Burst DMA timing.

tRHSH

tSLRL

tSHAH

SV00874

SV00875

Fig 21. DMA terminated by EOT.

9397 750 09238

Product data

Rev. 08 — 20 December 2001

© Koninklijke Philips Electronics N.V. 2001. All rights reserved.

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