PDIUSBD12 Ver la hoja de datos (PDF) - Philips Electronics
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PDIUSBD12 Datasheet PDF : 35 Pages
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Philips Semiconductors
PDIUSBD12
USB interface device with parallel bus
Table 17: AC characteristics (parallel interface)
Symbol Parameter
ALE timings
tLH
ALE HIGH pulse width
tAVLL
address valid to ALE LOW time
tLLAX
ALE LOW to Address transition time
Write timings
tCLWL
tWHCH
tAVWL
CS_N (DMACK_N) LOW to WR_N LOW time
WR_N HIGH to CS_N (DMACK_N) HIGH time
A0 Valid to WR_N LOW time
Conditions
tWHAX
WR_N HIGH to A0 transition time
tWL
WR_N LOW pulse width
tWDSU
tWDH
write data setup time
write data hold time
tWC
write cycle time
t(WC - WD) write command to write data
Read timings
tCLRL
CS_N (DMACK_N) LOW to RD_N LOW time
tRHCH
tAVRL
tRL
tRLDD
tRHDZ
tRC
t(WC - RD)
RD_N HIGH to CS_N (DMACK_N) HIGH time
A0 Valid to RD_N LOW time
RD_N LOW pulse width
RD_N LOW to Data Driven time
RD_N HIGH to Data Hi-Z time
read cycle time
write command to read data
[1] Can be negative.
[2] For DMA access only on the module 64th byte and the second last (EOT-1)byte.
[3] The tWC and tRC timings are valid for back-to-back data access only.
Min
Max Unit
20
−
ns
10
−
ns
−
10
ns
0 [1]
−
ns
5
−
ns
0 [1]
−
ns
130[2] -
ns
5
−
ns
20
−
ns
30
−
ns
10
−
ns
500[3] −
ns
600
-
ns
0 [1]
−
ns
130[2] -
ns
5
−
ns
0 [1]
−
ns
20
−
ns
−
20
ns
−
20
ns
500[3] −
ns
600
-
ns
Fig 17. ALE timing.
9397 750 09238
Product data
Rev. 08 — 20 December 2001
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
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