PCF2119VU-2-F2 Ver la hoja de datos (PDF) - NXP Semiconductors.

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PCF2119VU-2-F2

LCD controllers/drivers

NXP Semiconductors. 

NXP Semiconductors

PCF2119x

LCD controllers/drivers

10.2.3.3 Icon_ctl

Table 25. Icon_ctl bit description

Bit

Symbol

Value

RS

-

0

R/W -

0

7 to 3 -

0000 1

2

IM

0

1

1

IB

0

1

0

DM

0

1

Description

see Table 10

fixed value

icon mode

character mode, full display

icon mode, only icons displayed

icon blink

icon blink disabled

icon blink enabled

direct mode

off

on

The PCF2119x can drive up to 160 icons. See Figure 21 and Figure 22 for CGRAM to

icon mapping.

Bit IM: When bit IM = 0, the chip is in character mode. In the character mode characters

and icons are driven (multiplex drive mode 1:18 or 1:9). The VLCD generator, if used,

produces the VLCDOUT voltage programmed with register VA.

When bit IM = 1, the chip is in icon mode. In the icon mode only the icons are driven

(multiplex drive mode 1:2). The VLCD generator, if used, produces the VLCDOUT voltage as

programmed with register VB.

Table 26. Normal/icon mode operation

Bit IM Mode

0

character mode

1

icon mode

VLCDOUT

generated from VA

generated from VB

Bit IB: Icon blink control is independent of the cursor/character blink function.

When bit IB = 0, the icon blink is disabled. Icon data is stored in CGRAM character 0 to 3

(4 × 8 × 5 = 160 bits for 160 icons).

When bit IB = 1, the icon blink is enabled. In this case each icon is controlled by two bits.

Blink consists of two half phases (corresponding to the cursor on and off phases called

even and odd phases hereafter).

Icon states for the even phase are stored in CGRAM characters 0 to 3

(4 × 8 × 5 = 160 bits for 160 icons). These bits also define icon state when icon blink is not

used (see Table 27).

Icon states for the odd phase are stored in CGRAM character 4 to 7 (another 160 bits for

the 160 icons). When icon blink is disabled CGRAM characters 4 to 7 may be used as

normal CGRAM characters.

PCF2119X_5

Product data sheet

Rev. 05 — 13 August 2009

© NXP B.V. 2009. All rights reserved.

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