PCF2113 Ver la hoja de datos (PDF) - NXP Semiconductors.

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Fabricante

PCF2113

LCD controllers/drivers

NXP Semiconductors. 

NXP Semiconductors

PCF2113x

LCD controllers/drivers

Icon states for the even phase are stored in CGRAM characters 0 to 2

(3 × 8 × 5 = 120 bits for 120 icons). These bits also define icon state when icon blink is not

used (see Table 13).

Icon states for the odd phase are stored in CGRAM characters 4 to 6 (another 120 bits for

the 120 icons). When icon blink is disabled CGRAM characters 4 to 6 may be used as

normal CGRAM characters.

Table 13. Blink effect for icons and cursor character blink

Parameter

Even phase

Odd phase

Cursor character blink block (all on)

normal (display character)

Icons

state 1; CGRAM character 0 to 2 state 2; CGRAM character 4 to 6

10.5 Direct mode

When DM = 0, the chip is not in the Direct mode. Either the internal VLCD generator or an

external voltage may be used to achieve VLCD.

When DM = 1, the chip is in Direct mode. The internal VLCD generator is turned off and the

output VLCDOUT is directly connected VDD2 (i.e. the VLCD generator supply voltage).

The Direct mode can be used to reduce the current consumption when the required

output voltage VLCDOUT is close to the VDD2 supply voltage. This can be the case in Icon

mode or in MUX 1:9 (depending on LCD liquid properties).

10.6 Voltage multiplier control

10.6.1 Bits S1 and S0

A software configurable voltage multiplier is incorporated in the VLCD generator and can

be set via the ‘Set HVgen stages’ command.

The voltage multiplier control can be used to reduce current consumption by

disconnecting internal voltage multiplier stages, depending on the required output voltage

VLCD (see Table 14).

Table 14.

S1

0

0

1

1

S1 and S0 control of voltage multiplier

S0

Description

0

set VLCD generator stages to 1 (2 × voltage multiplier)

1

set VLCD generator stages to 2 (3 × voltage multiplier)

0

set VLCD generator stages to 3 (4 × voltage multiplier)

1

do not use

10.7 Screen configuration

10.7.1 Bit L

L = 0: the two halves of a split screen are connected in a standard way i.e. column 1/61,

2/62 to 60/120; default.

L = 1: the two halves of a split screen are connected in a mirrored way i.e. column 1/120,

2/119 to 60/61. This allows single layer PCB or glass layout.

PCF2113_FAM_4

Product data sheet

Rev. 04 — 4 March 2008

© NXP B.V. 2008. All rights reserved.

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