PCF8558 Ver la hoja de datos (PDF) - Philips Electronics
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PCF8558 Datasheet PDF : 24 Pages
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Philips Semiconductors
Universal LCD driver for small graphic
panels
Objective specification
PCF8558
AC CHARACTERISTICS
All timing values are referenced to VIH and VIL levels with an input voltage swing of VSS to VDD. VDD = 2.5 to 6 V;
VSS = 0 V; VLCD = VDD − 3.5 V to VDD − 9 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
fFR)
fOSC(ext)
tPLCD
LCD frame frequency
(internal oscillator)
external clock frequency
driver delays
VDD − VLCD = 9 V;
with test loads
37
62.5 94
Hz
90
150
225
kHz
−
−
100
µs
I2C-bus (see Fig.12)
fSCL
SCL clock frequency
−
−
tCLKL
SCL LOW time
1.3
−
tCLKH
SCL HIGH time
0.6
−
tBUF
bus free time
between successive STOP 1.3
−
and START conditions
tr
tf
tSU;STA
tHD;STA
tSU;DAT
tHD;DAT
tSU;STO
tSW
Cb
SCL and SDA rise time
SCL and SDA fall time
START condition set-up time
START condition hold time
data set-up time
data hold time
STOP condition set-up time
tolerable spike width on bus
capacitive load per bus line
note 1
note 1
repeated start codes only
note 2
−
−
20 + 0.1Cb −
0.6
−
0.6
−
100
−
0
−
0.6
−
−
−
−
−
400
kHz
−
µs
−
µs
−
µs
300
ns
300
ns
−
µs
−
µs
−
ns
−
ns
−
µs
50
ns
400
pF
Notes
1. The rise and fall times specified here refer to the driver device (i.e. not PCF8558) and are part of the general fast
I2C-bus specification. However, when PCF8558 asserts an acknowledge on SDA, the fall time is given by parameter
tf. Cb = capacitive load per bus line.
2. The device inputs SDA and SCL are filtered and will reject spikes on the bus lines of width <tSW(max).
handbook, full pagewidth
1998 Apr 07
1 nF
R1 to R40,
C1 to C101
SDA
1.5 kΩ
VDD
MGG564
Fig.11 AC test loads.
15
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